isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 46

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
9.14 Aborting transfers
9.15 Avoiding contention on the ULPI data bus
The ISP1504x1 supports aborting transfers on the ULPI bus. For details, refer to UTMI+
Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 .
Because the ULPI data bus is bidirectional, avoid situations in which both the link and the
PHY simultaneously drive the data bus.
The following points must be considered while implementing the data bus drive control on
the link.
After power-up and clock stabilization, default states are as follows:
When the ISP1504x1 wants to take control of data bus to initiate a data transfer, it
changes the DIR value from LOW to HIGH.
At this point, the link must disable its output buffers. This must be as fast as possible so
the link must use a combinational path from DIR.
The ISP1504x1 will not immediately enable its output buffers, but will delay the enabling of
its buffers until the next clock edge, avoiding bus contention.
When the data transfer is no longer required by the ISP1504x1, it changes DIR from HIGH
to LOW and starts to immediately turn off its output drivers. The link senses the change of
DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,
avoiding data bus contention.
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The ISP1504x1 drives DIR to LOW.
The data bus is input to the ISP1504x1.
The ULPI link data bus is output, with all data bus lines driven to LOW.
Rev. 01 — 6 August 2007
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
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