isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 36

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
Fig 15. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1504x1 operates just as in full-speed mode, and sends all data with full-speed rise and
fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1504x1
will automatically send a preamble header at full-speed bit rate before sending the link
packet at low-speed bit rate. The ISP1504x1 will ensure a minimum gap of four full-speed
bit times between the last bit of the full-speed PRE PID and the first bit of the low-speed
packet SYNC. The ISP1504x1 will drive a J for at least one full-speed bit time after
sending the PRE PID, after which the pull-up resistor can hold the J state on the bus. An
example transmit packet is shown in
In preamble mode, the ISP1504x1 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 01 — 6 August 2007
link decision time (1 to 14 clocks)
Figure
IDLE
ISP1504A1; ISP1504C1
16.
ULPI HS USB OTG transceiver
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2007. All rights reserved.
SYNC
D0
004aaa713
36 of 80
D1