isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 32

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each
than 7 ms after reset time T
up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks
and Js. Each Chirp K or Chirp J must last no less than 40 s and no longer than
60 s.
Chirp K and Chirp J must be detected for at least 2.5 s. After seeing that
minimum sequence, the peripheral sets TERMSELECT = 0b and OPMODE[1:0] =
00b. The peripheral is now in high-speed mode and sees !squelch (01b on
LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows
that the host has completed chirp and waits for high-speed USB traffic to begin.
After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and
begins sending USB packets.
Rev. 01 — 6 August 2007
0
. If the peripheral is in low-power mode, it must wake
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
32 of 80