isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 31

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
Fig 11. Example of register write, register read, extended register write and extended register read
DATA[7:0]
CLOCK
NXT
AD indicates the address byte, and D indicates the data byte.
STP
DIR
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
register write
TXCMD
immediate
Figure 11
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1504x1 asserts
DIR during the operation. When a register operation is aborted, the link must retry until
successful. For more information on register operations, refer to UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1 .
Figure 12
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates, and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register and setting XCVRSELECT[1:0] =
00b (high-speed) and TERMSELECT = 0b, which drives SE0 on the bus (DP and DM
are connected to ground through 45 ). The host also sets OPMODE[1:0] = 10b for
correct chirp transmit and receive. The start of SE0 is labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The Host Controller must interpret LINESTATE as shown
in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
Table
capable of high-speed, it sets XCVRSELECT[1:0] to 00b (high-speed) and
OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
shows register read and write sequences. The ISP1504x1 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
13.
extended
Rev. 01 — 6 August 2007
TXCMD
(REGR)
register read
immediate
D
ISP1504A1; ISP1504C1
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
0
.
Figure 12
© NXP B.V. 2007. All rights reserved.
004aaa710
does not
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