peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 103
peb20534h-52
Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20534H-52.pdf
(439 pages)
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Figure 26
The external bus cycles of the EBC can be extended for a memory or peripheral, which
cannot keep pace with the EBC’s maximum speed, by introducing wait states during the
access (see figure above).
The minimum LRD/LWR strobe active length is 2 LBI clock cycles (with zero MCTC wait
states).
The memory cycle time wait states can be programmed in increments of one EBC
system clock (LCLKO) within a range from 0 to 15 (default value after reset) via the
’MCTC’ bit field in the LBI Configuration register LCONF. (15-<MCTC>) waitstates will
be inserted.
Data Sheet
LALE
Data IN
LRD
Data OUT
LWR
Memory Cycle Time
Address
Address
103
Data
MCTC Wait States (1...15)
Multi Function Port (MFP)
PEB 20534
PEF 20534
Data
2000-05-30
ITD10613
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