peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 136

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

In this case a useful sequence of clearing the SCC receive FIFO during operation is:
Data Sheet
Register Bit field
CCR2
CMDR
CMDR
CCR2
RAC=’0’
RRES=’1’ Resets the receive protocol logic and clears the SCC
RFRD=’1’ Generates a frame end indication which is transferred to the
RAC=’1’
Description
Switches the receive protocol logic to inactive state not
accepting any more data from the serial line.
receive FIFO (self-resetting command bit).
central RFIFO terminating any partial frame. If no partial
frame was stored, this will result in a "frame" with byte
number zero.
Switches the receive protocol logic to active state accepting
receive data from the serial line.
Serial Communication Controller (SCC) Cores
136
PEB 20534
PEF 20534
2000-05-30