peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 294

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
TLP
SFLAG
TOIE
Test Loop
This bit controls the internal test loop between transmit and receive data
signals. The test loop is closed at the far end of serial transmit and
receive line just before the respective TxD and RxD pins:
TLP = ’0’
TLP = ’1’
Shared Flags Transmission
This bit enables ’shared flag transmission’ in HDLC protocol mode. If
another transmit frame begin is stored in the SCC transmit FIFO, the
closing flag of the preceding frame becomes the opening flag of the next
frame (shared flags):
SFLAG = ’0’ Shared flag transmission disabled.
SFLAG = ’1’ Shared flag transmission enabled.
Note: The receiver always supports shared flags and shared zeros of
Time Out Indication Enable
If this bit is selected in ASYNC mode, any time out event will
automatically generate a ’RFRD’ command thus inserting a ’frame end/
block end’ indication into the receive FIFO. This causes the SCC receive
FIFO to forward received data to the DMA Controller even if the receive
FIFO threshold is not exceeded. The DMA controller is forced to finish
the current receive descriptor with an ’frame end / block - end’ indication:
TOIE = ’0’
TOIE = ’1’
consecutive flags.
Test loop disabled.
Test loop enabled.
The software is responsible to select a clock mode which
allows correct reception of transmit data depending on the
external clock supply. Transmit data is also sent out via
pin TxD, but receive input pin RxD is internally
disconnected during test loop operation.
Note: It is recommended not to use the test loop in high
Automatic Time Out processing disabled.
Automatic Time Out processing enabled.
speed operation mode (clock mode 4). A non high
speed clock mode should be selected for test loop
operation.
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Detailed Register Description
(async mode)
PEB 20534
PEF 20534
(hdlc mode)
(all modes)
2000-05-30