peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 224
peb20534h-52
Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20534H-52.pdf
(439 pages)
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Table 41
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Note: Bit locations containing a ’0’ or ’1’ are hardwired status and configuration settings
Data Sheet
Bit 31
Bit 15
0
specifying a fixed device behavior. These bit locations are also described in
Table
30
14
0
42.
PCI Configuration Space: Status/Command Register
29
13
0
28
12
0
read/write (PCI Configuration Cycles)
0280 000
04
written by CPU
evaluated by DSCC4
H
(PCI Configuration Space Offset Address)
27
11
0
0
H
26
10
0
0
PCI Status Information
25
PCI Command Bits
9
1
24
224
8
23
7
1
0
22
6
0
Detailed Register Description
21
5
0
0
20
0
4
0
19
0
3
18
0
2
PEB 20534
PEF 20534
2000-05-30
17
0
1
16
0
0
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