peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 358
peb20534h-52
Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20534H-52.pdf
(439 pages)
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Data Sheet
SSCREN
SSCRE
SSCTEN
SSCTE
SSCPO
SSC Receive Error Enable
This bit selects whether the SSC ignores or checks receive errors:
SSCREN
=’0’
SSCREN
=’1’
SSC Receive Status Flag
This bit indicates a receive error:
SSCRE=’0’
SSCRE=’1’
SSC Transmit Error Enable
This bit selects whether the SSC ignores or checks transmit errors:
SSCTEN
=’0’
SSCTEN
=’1’
SSC Transmit Status Flag
This bit indicates a transmit error:
SSCTE=’0’
SSCTE=’1’
SSC Polarity Control
This bit selects the polarity of the clock:
SSCPO=’0’
SSCPO=’1’
The SSC ignores receive errors.
The SSC checks receive errors.
No receive error is detected.
A receive error is detected, i.e. reception is completed
before the receive buffer was read by the CPU.
The SSC ignores transmit errors.
The SSC checks transmit errors.
No transmit error is detected.
A transmit error is detected, i.e. transmission starts before
the transmit buffer has been updated by the CPU.
The idle clock line is ’low’. Leading clock edge is a low-to-
high transition.
The idle clock line is ’high’. Leading clock edge is a high-
to-low transition.
358
Detailed Register Description
(configuration mode)
(configuration mode)
(configuration mode)
(operation mode)
(operation mode)
PEB 20534
PEF 20534
2000-05-30
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