peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 217
peb20534h-52
Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20534H-52.pdf
(439 pages)
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Table 37
Register
SCC1 resets transmitter and receiver. After transmitter reset an XPR interrupt is
generated. A corresponding interrupt vector is forwarded through the interrupt
queue to the appropriate interrupt ring buffer in shared memory.
GSTAR
GSTAR
1st entry of
IQSCC1TX in
shared memory
CH1CFG
CH1BRDA
CH1BTDA
GCMDR
DSCC4 checks the CHiCFG registers and performs the configuration of the DMA
channels as required. After configuration an appropriate interrupt vector is
generated and forwarded to IQCFG in shared memory
After configuration the DMAC transfers transmit data from the tx data buffer to the
central TFIFO. These data are forwarded to the SCC1, which loops back the data
at the serial port . The received data are forwarded to the central RFIFO. Then the
DMAC transfers the receive data to the rx data buffer in shared memory.
The data transmission is completed with appropriate interrupts: ALLS, RFS, HI, FI.
GSTAR
GSTAR
Data Sheet
Register Initialization for HDLC Transparent Mode 0, Test Loop
Access
<= (write)
=> (read)
=>
<=
=>
<=
<=
<=
<=
=>
<=
Value
0200 0000
0200 0000
5200 1000
0018 0000
0001 0000
0001 1000
0000 0001
2220 0001
2220 0001
217
Meaning
Indication Bit:
- SCC1 TX interrupt indicated
Indicated interrupt is acknowledged.
Indication Bits:
- SCC1 TX interrupt queue ID
- Caused by SCC
- XPR interrupt indicated
Configuration of DMAC channels:
- Enable all interrupts: RFI, TFI, RERR,
TERR
-Set commands: IDR, IDT
Set base receive descriptor address.
(See figure 75.)
Set base transmit descriptor address.
(See figure 75.)
Command Bit:
- Action Request
Indication Bits:
- SCC1 RX interrupt indicated
- SCC1 TX interrupt indicated
- CFG interrupt indicated
- Action Request Acknowledge indicated
Indicated interrupts are acknowledged.
Reset and Initialization Procedure
PEB 20534
PEF 20534
2000-05-30
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