fin12a Fairchild Semiconductor, fin12a Datasheet - Page 13

• Manufacturer Part Number: fin12a
• Description: Fin12a Mserdes Low Voltage 12-bit Bi-directional Serializer/deserializer With Multiple Frequency Ranges Preliminary
• Manufacturer: Fairchild Semiconductor

t
t
t
t
t
t
t
t
t
t
TLH
THL
STC
HTC
TCCD
SK(P-P)
t
t
t
t
t
t
t
t
Serializer AC Electrical Characteristics
Serializer Timing Characteristics
Note 6: Skew is measured from either the rising or falling edge of the bit clock (CKSO) relative to the rising or falling edge of the data bit (DSO). CKSO and
DSO have been designed to be edge aligned.
PLL Specifications
JCC
TPLLS0
TPLLD0
TPLLD1
Note 7: This jitter specification is based on the assumption that PLL has a Ref Clock with cycle-to-cycle input jitter less than 2ns.
Note 8: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The
specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Deserializer AC Electrical Characteristics
Note 9: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state.
Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew
from the serializer, load variations and ISI and jitter effects.
Note 10: Rising edge of CKP will appear approximately 7-bit times after the falling edge of the CKP output. Data will appear coincident with this falling edge.
Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to STROBE for the serializer the
CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain in 7 bit times.
S_DS
H_DS
RCOP
RCOL
RCOH
PDV
ROLH
ROHL
Symbol
Symbol
Symbol
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
DP[n] Setup to STROBE
DP[n] Hold to STROBE
Transmitter Clock Input to
Clock Output Delay
CKSO Position Relative to DS
CKSO Clock Out Jitter (Cycle-to-Cycle)
Serializer Phase Lock Loop Stabilization Time See Figure 20
PLL Disable Time Loss of Clock
PLL Power-Down Time
Serial Port Setup Time DS to CKSI
Serial Port Hold Time DS to CKSI
Deserializer Clock Output (CKP OUT) Period See Figure 19
CKP OUT Low Time
CKP OUT High Time
Data Valid to CKP HIGH
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Parameter
Parameter
Parameter
See Figure 15
DIRI
See Figure 17 (f 10 MHz)
See Figure 21, DIRI
CKREF
See Figure 24, (Note 6)
CKREF Serialization Mode
See Figure 24, (Note 6)
No CKREF Serialization Mode
See Figure 23, (Note 9)
See Figure 23, (Note 9)
See Figure 19 (Rising Edge Strobe)
Serializer Source STROBE
Where a
See Figure 19 (Rising Edge Strobe)
Where a
C
See Figure 16
(Note 7)
See Figure 25, (Note 8)
See Figure 26
L
1
8pF
Test Conditions
STROBE
Test Conditions
Test Conditions
(1/f)/14 (Note 10)
(1/f)/14 (Note 10)
13
1,
CKREF
Min
TBD
TBD
TBD
Min
3.0
2.5
0

7a
7a
7a
17.8
Min
500
500



3
3
3
TBD
Typ
TBD
TBD
TBD
Typ
0.6
0.6
Typ
3.5
3.5
7a
T
www.fairchildsemi.com
Preliminary
1000
Max
10.0
20.0
TBD
TBD
TBD
Max
7a
7a
7a
Max
0.9
0.9
200
7.0
7.0



3
3
3
Cycles
Units
Units
Units
ns
us
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps