sta381bws STMicroelectronics, sta381bws Datasheet
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... STSpeakerSafe – Pre and post processing DC blocking filters – Checksum engine for filter coefficients – PWM fault self-diagnosis ■ STCompressor Table 1. Order code STA381BWS STA381BWSTR Doc ID 018937 Rev 2 STA381BWS Sound Terminal Preliminary data VQFN48 ( mm DRC) TM protection circuitry: TM dual-band DRC ...
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... STC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Band splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Dynamic attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Stereo link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Programming of coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS 5.1.2 5.1.3 5.1.4 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.1 5.3.2 5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 6 Register description: New Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 CLK register (addr 0x00 6.2 STATUS register (addr 0x01 6.3 RESET register (addr 0x02 6.4 Soft volume register (addr 0x03 6.5 MVOL register (addr 0x04 6.6 FINEVOL register (addr 0x05 6.7 CH1VOL register (addr 0x06 ...
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... External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Mute/line output configuration register (addr 0x17 Channel 3 / line output volume (addr 0x1B interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS 6.22 Tone control register (addr 0x22 6.22.1 6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46 6.23.1 6.23.2 6.23.3 6.23.4 6.23.5 6.23.6 6.23.7 6.23.8 6.24 User-defined coefficient control registers (addr 0x27 - 0x37 6.24.1 6.24.2 6.24.3 6.24.4 6.24.5 6.24.6 6.24.7 6.24.8 6.24.9 6.24.10 Coefficient a1 data register bits 7 6.24.11 Coefficient a2 data register bits 23: 6.24.12 Coefficient a2 data register bits 15 6.24.13 Coefficient a2 data register bits 7 6.24.14 Coefficient b0 data register bits 23: ...
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... Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 111 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS 7.4.2 7.4.3 7.4.4 7.4.5 7.5 Configuration register E (addr 0x04 112 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 Configuration register F (addr 0x05 114 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.7 Volume control registers (addr 0x06 - 0x0A 121 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.8 Audio preset registers (addr 0x0C 124 7.8.1 7.8.2 7.8.3 7.9 Channel configuration registers (addr 0x0E - 0x10 125 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.10 Tone control register (addr 0x11 127 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Zero-detect mute enable ...
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... Coefficient b1 data register bits 15 133 Coefficient b1 data register bits 7 133 Coefficient b2 data register bits 23: 134 Coefficient b2 data register bits 15 134 Coefficient b2 data register bits 7 134 Coefficient a1 data register bits 23: 134 Coefficient a1 data register bits 15 134 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS 7.16.2 7.16.3 7.16.4 7.17 EQ soft volume configuration registers (addr 0x37 - 0x38 144 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40 145 7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46 146 7.20 Short-circuit protection mode registers SHOK (address 0x47 148 7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A 149 7 ...
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... Table 40. Post-scale link Table 41. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 42. Zero-detect mute enable Table 43. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 44. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 45. AM mode enable Table 46. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 47. Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 48. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10/168 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS Table 49. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 50. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 51. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 52. IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 53. External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 54. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 55. Mute configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 56. Channel 3 volume as a function of CH3VOL[7: Table 57. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 58 ...
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... Table 150. Limiter attack threshold as a function of LxAT bits (DRC mode 132 Table 151. Limiter release threshold as a function of LxRT bits (DRC mode 132 Table 152. RAM block for biquads, mixing, scaling and bass management 139 12/168 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS Table 153. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 154. Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 155. Extended attack rate, limiter 143 Table 156. Extended attack rate, limiter 143 Table 157. Extended biquad selector, biquad 143 Table 158. Extended biquad selector, biquad 143 Table 159 ...
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... Figure 45. F3X (from SAI) source to line/headphone out application scheme 162 Figure 46. F3X auxiliary analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 47. Headphone and line out block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 48. Output configuration for stereo BTL mode in filterlight configuration . . . . . . . . . . . . . . . . 164 14/168 2 DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS Figure 49. VQFN48 ( 0.9 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Doc ID 018937 Rev 2 List of figures 15/168 ...
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... SW channel can be also driven through the PWM output. The STA381BWS is able to deliver (ternary) into an 8 Ω load (binary) into a 4 Ω load plus (ternary) into an 8 Ω load ...
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... STA381BWS 1.1 Block diagram Figure 1. Block diagram MCLK LRCKI BICKI SDI LINEINL LINEINR TESTMODE PWDN INTLINE RESET SA SDA SCL STA381BWS STA381BW 2.1 Channel Audio Processor FFX TM Modulator TM STAudioFx TM STSpeakerSafe Parametric EQ Binary Volume Ternary Bass and Treble Speaker Compensation Stereo Widening Control logic & ...
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... Figure 2. Pin connections VQFN48 (top view) VCC_REG 1 VSS_REG 2 OUT2B 3 GND2 4 VCC2 5 OUT2A 6 OUT1B 7 8 VCC1 GND1 9 10 OUT1A VDD_REG 11 GND_REG 12 18/168 STA381BWS STA381BW Doc ID 018937 Rev 2 STA381BWS 36 MCLK AGNDPLL 35 VREGFILT 34 33 TWARNEXT/FFX4B 32 EAPD/FFX4A FFX3B 31 30 FFX3A 29 GNDDIG1 28 VDDDIG1 27 VDD3V3CHP 26 CPP 25 GNDPSUB ...
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... STA381BWS 2.2 Pin description Table 2. Pin list VQFN 48-pin Name Type VCC_REG POWER VSS_REG POWER OUT2B OUTPUT GND2 POWER VCC2 POWER OUT2A OUTPUT OUT1B OUTPUT VCC1 POWER ...
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... TEST_MODE INPUT GNDDIG2 POWER VDDDIG2 POWER Not Connected N.C. Doc ID 018937 Rev 2 STA381BWS Description Digital PWM line out Digital PWM line out Digital PWM line out Digital VDD from core PLL analog ground PLL input clock IIS serial clock IIS left/right clock ...
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... STA381BWS 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Vcc Power supply voltage (VCCxA, VCCxB) VDD_DIG Digital supply voltage VDD3V3 Charge pump and analog path LDO supply Top Operating junction temperature Tstg Storage temperature R Load impedance - line driver mode ...
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... V Low level output voltage ol V High level output voltage oh R Pull-up/down resistance pu 22/168 Parameter = 25° C. amb Parameter Conditions VDD_DIG = 3.3 V Iol = 2 mA Ioh = 2 mA Doc ID 018937 Rev 2 STA381BWS Min Typ Max Unit 4.5 25.5 V 2.7 3.3 3.6 V 2.7 3.3 3 ° kΩ Ω ...
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... STA381BWS 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol Parameter Output power BTL Po Output power Ω Output power Power Pchannel/Nchannel MOSFET ...
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... Line out mode Vrms Out HP mode 200 out RMS Line out mode 0.2 Vrms, G Out , Figure 47: Headphone and line out block Doc ID 018937 Rev 2 STA381BWS = 32 Ω, unless otherwise specified. Min Typ Max Unit 1.9 2.1 Vrms 40 mW 100 ( ...
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... Bass and Treble controls (BQL=0, BQ5=0, BQ6=0, BQ7=0). The STA381BWS offers the possibility to share the filter coefficients between the two processing channels. When this option is set (BQL=1), filters from the 1st to the 4th have the same coeffcients set. Under these conditions, filters from the 5th to 7th can be used as custom filters as well (provided the relevant BQx bits are set) ...
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... -------------- Vo lume Lo w-p ass XO filter C3Mx2 U s er-D efined C ros sov er F requenc oeffic ients D eterm ined by XO Setting (User Defin =0000) Doc ID 018937 Rev 2 STA381BWS (Figure 5): two individually ® products. An ti-clipper DC Cut / Po st Scale Filter DRC An ti-clipper DC Cut / ...
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... Volume filter C2Mx2 C3Mx1 Channel 3 Volume + C3Mx2 User-Defined Crossover Frequency Mix Coefficients Determined by XO Setting (User Defined If XO=0000) TM (Figure 7): the STA381BWS embeds the latest, state- Section 4.3: STCompressorTM TM C1Mx1 Channel ½ Biquad #8 + -------------- STCompressor Hi-pass XO Filter C1Mx2 C2Mx1 Channel ½ Biquad #8 + -------------- ...
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... STC filters from erroneous coefficients downloads, thus improving the final application circuitry and safety of the speakers. 28/168 TM TM (STC from now on stereo, dual-band Dynamic Range Control Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS 4.3.1 STC block diagram Figure 8. STCompressor Ban d Sp litter (Lo w freq Ban d Sp litter (Hig h freq s) The STC takes as input 2 channels and every channel is processed independently (i.e. an independent DRC for each band of each channel) following the steps listed below ...
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... CEXT_Bx[ order filtering Band Splitter Doc ID 018937 Rev 2 STA381BWS Table 9. The range Range [-1;1) [-2;2) [-4;4) Reserved Band 0 … Output Band 1 … ...
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... STA381BWS The STC reacts differently depending on these three parameters ● level meter output value < compressor threshold < limiter threshold: under these circumstances the signal level is small enough to not require any type of limiting/compressing action. The signal remains unchanged. ● compressor threshold < level meter output value < limiter threshold: under these circumstances the signal level is compressed to a ratio determined by the compressor rate ...
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... Device overview Figure 11. STCompressor Table 10. Compressor ratio Compressor ratio 32/168 TM behavior as a limiter Doc ID 018937 Rev 2 STA381BWS Ratio value 1:1 1:1.25 1:1.5 1:1.75 1:2 1:2.5 1:3 1:3.5 1:4 1:4.5 1:5 1:5.5 1.6 1:7 1:8 1:16 ...
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... STA381BWS 4.3.5 Attenuator The attenuation is characterized by two different phases: attack and release. Given an input signal above the limiter threshold, during the attack phase the STC decreases the gain in order to reach the output level determined by the mapper. In this process the key parameter is the attack rate (dB/ms) which determines how fast the STC ...
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... When the stereo link is active, the proper attenuation for each band is independently computed, then the highest one for each band is applied 34/168 12). On the other side, the traditional volume control is located after Doc ID 018937 Rev 2 STA381BWS (Figure 13). ...
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... STA381BWS Figure 13. Stereo link block diagram Ch 0 – Band 0 From mapper Ch 0 – Band 0 From mapper Ch 0 – Band – Band – Band 0 From mapper Ch 1 – Band 0 From mapper Ch 1 – Band – Band 1 4.3.9 Programming of coefficients The coefficients are expressed in different value ranges and in decimal notation (see the above paragraphs) ...
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... Device overview Table 11. Conversion example Original value (dec) 36/168 +48.00 +24.00 +16.00 +12.00 +06.00 +02.00 +01.00 -01.00 -02.00 -06.00 -12.00 -24.00 -48.00 Doc ID 018937 Rev 2 STA381BWS value (hex) 0x600000 0x300000 0x200000 0x180000 0x0C0000 0x040000 0x020000 0xFE0000 0xFC0000 0xF40000 0xE80000 0xD00000 0xA00000 ...
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... STA381BWS 4.3.10 Memory map All the control parameters listed in the previous paragraphs are stored in the internal device memory. Please refer to For the programming procedure please refer to control registers (addr 0x27 - the STC coefficients memory. Table 12. STC coefficients memory map Function Address 0x54 ...
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... B0/2 0x4F B1/2 0x50 B2 0x51 -A1/2 0x52 -A2 0x53 B0/2 Doc ID 018937 Rev 2 STA381BWS Range Default [-1, 1), [-2, 2), [-4, 4) 0x000000 [-1, 1), [-2, 2), [-4, 4) 0x000000 [-1, 1), [-2, 2), [-4, 4) 0x000000 [-1, 1), [-2, 2), [-4, 4) 0x000000 [-1, 1), [-2, 2), [-4, 4) 0x100000 [-1, 1), [-2, 2), [-4, 4) 0x000000 [-1, 1), [-2, 2), [-4, 4) 0x000000 ...
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... SA port configuration, 0x38 when and 0x3A when The eighth bit (LSB) identifies read or write operation RW, this bit is set read mode and to 0 for write mode. After a START condition the STA381BWS identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during ...
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... After receiving the internal byte address, the STA381BWS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA381BWS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... STA381BWS 5.4.5 Write mode sequence Figure 14. Write mode sequence BYTE BYTE WRITE WRITE START START MULTIBYTE MULTIBYTE WRITE WRITE START START 5.4.6 Read mode sequence Figure 15. Read mode sequence CURRENT CURRENT DEV-ADDR DEV-ADDR ADDRESS ADDRESS READ READ START START RANDOM RANDOM DEV-ADDR DEV-ADDR ...
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... Register description: New Map Mapping of two registers is available on the STA381BWS, the selection is done by setting register 0x7E bit default, 0x7E is set to 1 and refers to a map that is not compatible with previous Sound Terminal devices. This register’s mapping is also called “New Map”. ...
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... STA381BWS Table 14. Default register map table: NEW MAP (continued) Addr Name D7 0x25 L2AR L2A3 0x26 L2ATRT L2AT3 0x27 CFADDR 0x28 B1CF1 C1B23 0x29 B1CF2 C1B15 0x2A B1CF3 C1B7 0x2B B2CF1 C2B23 0x2C B2CF2 C2B15 0x2D B2CF3 C2B7 0x2E A1CF1 C3B23 0x2F ...
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... LPDE PNDLSL[2:0] BPTH[5:0] BPTIM[7:0] HSEL[1:0] RMS_CH0[7:0] RMS_CH0[15:8] RMS_CH1[7:0] RMS_CH1[15:8] F3X_SM_SLOPE[2:0] BQ_CKE[7:0] BQ_CKE[15:8] BQ_CKE[23:16] XC_CKE[7:0] XC_CKE[15:8] XC_CKE[23:16] BQ_CKR[7:0] BQ_CKR[15:8] BQ_CKR[23:16] XC_CKR[7:0] XC_CKR[15:8] XC_CKR[23:16] Doc ID 018937 Rev 2 STA381BWS CPWMEN ZMTH[2:0] CPFEN CPOK ABFAULT F3X_MUTE NP_CRCR ES STC_LNK BCAUTO WRA D0 SHEN DCROK F3X_ENA CH12 ...
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... STA381BWS 6.1 CLK register (addr 0x00 Table 15. CLK register Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 0 R/W 6.2 STATUS register (addr 0x01 FAULT DRCCRC NA NA Table 16. STATUS register Bit R Fault status is set to 1 once the power bridge goes to tri-state mode. ...
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... SRESET ‘1’: reset the device D5 D4 Reserved Reserved 0 0 RST Name Description 00 01: 100 ms (default) SVOL[1:0] 10: 100 ms 11: Soft-mute disabled Doc ID 018937 Rev Reserved Reserved Reserved Description Reserved Reserved SVOL[1: STA381BWS D0 SRESET ...
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... STA381BWS 6.5 MVOL register (addr 0x04 Table 19. Master volume register Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R the volume is below -60 dB, the level will be approximated step. 6.6 FINEVOL register (addr 0x05 Reserved Reserved 0 0 Table 20. Fine volume register Bit R/W 1 R/W 0 R/W D5 ...
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... Name Description 0x00: mute CH1VOL[7:0] others: volume = [(CH1VOL-159)/ CH2VOL[7: RST Name Description 0x00: mute CH2VOL[7:0] others: volume = [(CH2VOL-159)/ Doc ID 018937 Rev 2 STA381BWS ( (1) ...
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... STA381BWS 6.9 POST scaler register (addr 0x08 Post scaler is set to POST/128 for both CH1 and CH2. 6.10 OPER register (addr 0x09 Reserved Reserved 0 0 Table 23. OPER register Bit R/W 1 R/W 0 R/W Table 24. OPER configuration selection OPER[1:0] 2-channel (full-bridge) power, 2-channel data-out: 1A/1B → 1A/1B 2A/2B → ...
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... Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half Bridge Bridge Channel 2 Channel 2 Half Half Bridge Bridge OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B Power Power Channel 3 Channel 3 Device Device EAPD EAPD Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS Figure 19. OPER = 01 The STA381BWS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries ...
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... In this configuration the PWM slot phase is the following as shown in Figure 21. 2.0 channels (OPER = 00) PWM slots 52/168 = 00) OPER OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B OUT4A OUT4A OUT4B OUT4B Doc ID 018937 Rev 2 STA381BWS Figure 21. ...
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... STA381BWS 2.1 channels, two half-bridges + one full-bridge ( ● FFX1A -> OUT1A ● FFX2A -> OUT1B ● FFX3A -> OUT2A ● FFX3B -> OUT2B ● FFX1A -> OUT3A ● FFX1B -> OUT3B ● FFX2A -> OUT4A ● FFX2B -> OUT4B ● FFX1A/1B configured as binary ● FFX2A/2B configured as binary ● FFX3A/3B configured as binary ● ...
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... In this configuration the PWM slot phase is the following as shown in Figure 23. 2.1 channels (OPER = 10) PWM slots OUT1A OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT1B OUT2A OUT2A OUT2A OUT2A OUT2B OUT2B OUT2B OUT2B OUT3A OUT3A OUT3A OUT3A OUT3B OUT3B OUT3B OUT3B 54/168 Doc ID 018937 Rev 2 STA381BWS = 10) OPER Figure 23. ...
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... R/W 1 R/W 0 R/W 6.11.1 Dual-band DRC The STA381BWS device provides a dual-band DRC (B data path, as depicted in 2 Figure 24. B DRC scheme L R The low frequency information (LFE) is extracted from the left and right channels, removing the high frequencies using a programmable Biquad filter, and then computing the difference ...
Page 56
... DRC can be configured specifying the cutoff frequency -alpha and ω ))/cos(ω is the cutoff frequency Figure 24) will have a symmetric (relative to the HP 2 DRC are the same as those described in 0x46). B Doc ID 018937 Rev 2 STA381BWS the corresponding low-pass 0 Section 6.23: Dynamic 2 DRC configure automatically the 2 DRC output. ...
Page 57
... R/W 0 R/W 1 R/W 2 R/W The STA381BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: ● 32.768 MHz for 32 kHz ● 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz ● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...
Page 58
... Internal interpolation ratio Bit R/W 4:3 R/W The STA381BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 3-times provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 30. ...
Page 59
... Serial data interface The STA381BWS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA381BWS always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12 ...
Page 60
... Right-justified 18-bit data 1110 0 Right-justified 16-bit data 2 0000 24-bit data 0001 0 Left-justified 16 to 24-bit data 0010 0 Right-justified 24-bit data 0110 0 Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data Doc ID 018937 Rev 2 STA381BWS Format Interface format ...
Page 61
... Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA381BWS work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that: ■ the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in ■ ...
Page 62
... Register description: New Map To avoid any audio side effects (like pop noise strongly recommended to soft mute any audio streams flowing into the STA381BWS data path before the desynchronization event happens. At the same time any processing related to the I only after the serial audio interface and the internal PLL are synchronous again. ...
Page 63
... DSP bypass Table 39. DSP bypass Bit R/W 2 R/W Setting the DSPB bit bypasses the EQ function of the STA381BWS. 6.16.2 Post-scale link Table 40. Post-scale link Bit R/W 3 R/W Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster ...
Page 64
... RST 3 R/W The STA381BWS features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately this mode, which is still greater than the SNR of AM radio. ...
Page 65
... STA381BWS 6.17.3 PWM speed mode Table 46. PWM speed mode Bit R/W RST 4 R/W 6.17.4 Zero-crossing enable Table 47. Zero-crossing enable Bit R/W RST 6 R/W The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero- crossing, no clicks are audible 6.18 Configuration register F (addr 0x16 EAPD PWDN 0 1 6.18.1 Invalid input detect mute enable Table 48 ...
Page 66
... LDTE LRCLK double trigger protection enable RST Name 0 ECLE Auto EAPD on clock loss RST Name 0: IC power-down low-power condition 1 PWDN 1: IC normal operation RST Name 0: External power stage power-down active 0 EAPD 1: Normal operation Doc ID 018937 Rev 2 STA381BWS Description Description Description Description ...
Page 67
... STA381BWS 6.19 Volume control registers (addr 0x17 - 0x1B) 6.19.1 Mute/line output configuration register (addr 0x17 LOC1 LOC0 0 0 Table 54. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. ...
Page 68
... The volume structure of the STA381BWS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -80 dB example, if CH3VOL = 0x00 or +48 dB and MVOL= -12 dB, then the total gain for channel 3 = +36 dB ...
Page 69
... STA381BWS 6.20 Audio preset registers (0x1D XO3 XO2 0 0 6.20.1 AM interference frequency switching Table 57. AM interference frequency switching bits Bit R/W 0 R/W Table 58. Audio preset AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 6.20.2 Bass management crossover Table 59. Bass management crossover Bit ...
Page 70
... Reserved Reserved C2BO C3LS1 C3LS0 C3BO Perform tone control on channel x - normal operation Bypass tone control on channel x Doc ID 018937 Rev 2 STA381BWS C1VPB C1EQBP C1TCB C2VPB C2EQBP C2TCB C3VPB Reserved ...
Page 71
... STA381BWS 6.21.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel. Table 62. EQ bypass CxEQBP 0 1 6.21.3 Volume bypass Each channel contains an individual channel volume bypass particular channel has ...
Page 72
... Channel x output source from Channel1 Channel 2 Channel TTC1 TTC0 BTC3 Boost/cut -12 dB -12 dB +12 dB +12 dB +12 dB Doc ID 018937 Rev 2 STA381BWS BTC2 BTC1 BTC0 … … ...
Page 73
... FFX amplifier. Since gain can be added digitally within the STA381BWS it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter ...
Page 74
... In anti-clipping mode, the attack and release thresholds are set relative to full-scale. In DRC mode (bit D0 reg 0x0A set to 1), the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. 74/168 Doc ID 018937 Rev 2 STA381BWS ...
Page 75
... STA381BWS Figure 25. Basic limiter and volume flow diagram Gain / Vo lume Table 68. Limiter attack rate as a function of LxA bits LxA[3:0] Attack rate dB/ms 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Limiter + Gain Atten uatio n 3 ...
Page 76
... AC (dB relative to fs) -12 - +10 Doc ID 018937 Rev 2 STA381BWS Table 71. Limiter release threshold as a function of LxRT bits (AC mode) LxRT[3:0] AC (dB relative to fs) 0000 -∞ 0001 -29 dB 0010 -20 dB 0011 -16 dB 0100 -14 dB 0101 -12 dB ...
Page 77
... STA381BWS Dynamic range compression mode Table 72. Limiter attack threshold as a function of LxAT bits (DRC mode) LxAT[3:0] DRC (dB relative to volume) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.23.5 Limiter 1 extended attack threshold (addr 0x43) ...
Page 78
... C1B21 C1B20 C1B19 C1B13 C1B12 C1B11 C1B5 C1B4 C1B3 Doc ID 018937 Rev 2 STA381BWS EATH2[2] EATH2[1] EATH2[ ERTH2[2] ERTH2[1] ERTH2[ CFA2 CFA1 CFA0 ...
Page 79
... STA381BWS 6.24.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 6.24.6 Coefficient b2 data register bits 15 C2B15 C2B14 0 0 6.24.7 Coefficient b2 data register bits 7 C2B7 C2B6 0 0 6.24.8 Coefficient a1 data register bits 23: C1B23 C1B22 0 0 6.24.9 Coefficient a1 data register bits 15 C3B15 C3B14 0 0 6.24.10 Coefficient a1 data register bits 7:0 ...
Page 80
... Coefficient write/read control register D7 D6 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA381BWS via RAM. Access to this RAM is available to the user via register interface. A collection of I contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...
Page 81
... STA381BWS Reading a coefficient from RAM 1. Write 6-bits of address Write bit Read top 8-bits of coefficient Read middle 8-bits of coefficient Read bottom 8-bits of coefficient in I Reading a set of coefficients from RAM 1. Write 6 bits of address Write bit ...
Page 82
... When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example 10, 20, 35 decimal), and the STA381BWS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. 82/168 2 C register 0x27 ...
Page 83
... STA381BWS 6.24.18 User-defined EQ The STA381BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0 ...
Page 84
... Channel 1 - Mix 1 0x39 Channel 1 - Mix 2 0x3A Channel 2 - Mix 1 0x3B Channel 2 - Mix 2 0x3C Channel 3 - Mix 1 0x3D Channel 3 - Mix 2 0x3E UNUSED 0x3F UNUSED Doc ID 018937 Rev 2 STA381BWS Coefficient Default C1H10(b1/2) 0x000000 C1H11(b2) 0x000000 C1H12(a1/2) 0x000000 C1H13(a2) 0x000000 C1H14(b0/2) 0x100000 C1H20 0x000000 … … ...
Page 85
... STA381BWS 6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D FDRC15 FDRC14 FDRC7 FDRC6 0 0 The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant ...
Page 86
... Limiter2 attack rate is 8 dB/ms Reserved User-defined biquad 5 coefficients are selected Pre-set bass filter selected as per User-defined biquad 6 coefficients are selected Pre-set treble filter selected as per User-defined biquad 7 coefficients are selected Table 74. Doc ID 018937 Rev 2 STA381BWS Mode Table 68 Mode Mode Table 67 Mode Table 67 ...
Page 87
... Reserved Reserved default, the STA381BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting The output PLL frequency formula is: where Fin is the input clock frequency from the pad. ...
Page 88
... PLL 0 PLL_BYP ‘1’: sys clock is from external pin (PLL is bypassed Normal behavior 0 OSC_PD 1 - Internal oscillator is in power-down ‘0’: Input oversampling selected by IR bits 0 BOOST32K ‘1’: Input oversampling is selected x3 Doc ID 018937 Rev 2 STA381BWS Description Description Description ...
Page 89
... Short-circuit protection mode registers SHOK (address 0x58 reserved reserved NA NA The following power bridge pins short-circuit protections are implemented in the STA381BWS: ● OUTxx vs. GNDx ● OUTxx vs. VCCx ● OUT1B vs. OUT2A The protection is enabled when reg. 0x50 bit 0 (SHEN) is set to ‘1’. The protection will check the short-circuit when the EAPD bit is toggled from ‘ ...
Page 90
... Biquads from have in the STA381BWS the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the use of high shelf filters that may require a coefficient dynamic greater in absolute value than 1. Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated. ...
Page 91
... Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5) A fadeout procedure is started in the STA381BWS once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down (tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the 13 million clock cycles ...
Page 92
... LPD] LPDE rid ge Fau lt ‘0 ’ Y LPD Doc ID 018937 Rev 2 STA381BWS Pin 32 output INT_LINE LPD E ...
Page 93
... BPTIM[ The STA381BWS implements a detection on PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect the DC level in the PWM outputs noted that the checks are performed on logic level PWM (i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs). ...
Page 94
... D6 N/A N/A The STA381BWS implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground. When active, the function will mute the output PWM when the input level become less than “ ...
Page 95
... STA381BWS Table 90. Zero-detect hysteresis HSEL[1: 6.33 Headphone/Line out configuration register (address 0x66 HPLN Reserved 0 0 Table 91. Headphone/Line out configuration bits Bit R/W 7 R Equivalent input level hysteresis(dB Reserved Reserved CPFEN 1 0 RST Name When F3X is connected to the internal HP/Line driver this bit selects the gain of the F3X-> ...
Page 96
... F3X_SM_SLOPE ‘100’: 200 ms 1 ‘101’: 250 ms ‘110’: 500 ms ‘111’: 1000 ms 1 F3X_MUTE ‘1’: Mute 0 F3X_ENA ‘1’: F3X enable Doc ID 018937 Rev 2 STA381BWS reserved reserved reserved F3X_MUTE 1 ...
Page 97
... STA381BWS 6.35 STCompressor 0x6C) Table 94. Register STCCFG0 D7 D6 Reserved Reserved 0 0 Table 95. STCCFG0 register Bit R/W 2 R/W Table 96. Register STCCFG1 D7 D6 Reserved Reserved 0 0 Table 97. STCCFG1 register Bit R/W 1 R/W TM configuration register (address 0x6B Reserved Reserved Reserved RST Name Description ‘0’ = CRC comparison successful ...
Page 98
... XCCKR[21] XCCKR[20] XCCKR[19 XCCKR[21] XCCKR[20] XCCKR[19 XCCMP XCGO BCAUTO Doc ID 018937 Rev 2 STA381BWS BQCKE[2] BQCKE[1] BQCKE[ BQCKE[10] BQCKE[9] BQCKE[ BQCKE[18] BQCKE[17] BQCKE[16 ...
Page 99
... MCU will handle this event ● Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA381BWS, on each audio frame, and reset event will be triggered in case of checksum mismatch. ● ...
Page 100
... D6 SMAP reserved 1 0 Table 98. Misc register 4 Bit R/W 7 R/W 1 R/W 0 R/W The STA381BWS allows direct access to the RAM coefficients bypassing the indirect access mechanism described in (addr 0x27 - 0x37). Direct access is implemented as follows. 100/168 D5 D4 reserved reserved 0 0 RST Name 1 SMAP ‘1’= NEW MAP, ‘0’= STMAP ‘ ...
Page 101
... Figure 30. Coefficients direct access single-read operation Please be aware that the STA381BWS supports 24-bit coefficients, for this reason in the above figures Coeff_x(0) is always equal to 0x00 when either reading or writing. The multi- write procedure embeds a wrap-around mechanism: when trying to write into a location exceeding the maximum coefficient address, the multi-write procedure will start from location 0x00 ...
Page 102
... C1B12 C1B6 C1B5 C1B4 C2B22 C2B21 C2B20 C2B14 C2B13 C2B12 C2B6 C2B5 C2B4 C3B22 C3B21 C3B20 C3B14 C3B13 C3B12 Doc ID 018937 Rev 2 STA381BWS IR0 MCS2 MCS1 SAI3 SAI2 SAI1 CSZ1 CSZ0 PSL DSPB AME NSBW BCLE IDE OCFG1 C3M C2M ...
Page 103
... STA381BWS 2 Table 99 registers summary (continued) 1F A1CF3 C3B7 20 A2CF1 C4B23 21 A2CF2 C4B15 22 A2CF3 C4B7 23 B0CF1 C5B23 24 B0CF2 C5B15 25 B0CF3 C5B7 26 CFUD 2B FDRC1 FDRC15 2C FDRC2 FDRC7 2D STATUS PLLUL 31 EQCFG XOB 32 EATH1 EATHEN1 33 ERTH1 ERTHEN1 34 EATH2 EATHEN2 35 ERTH2 ERTHEN2 36 CONFX MDRCE 37 SVCA 38 SVCB ...
Page 104
... LIM_BYP STC_ENA P BQ_CKE[7:0] BQ_CKE[15:8] BQ_CKE[23:16] XC_CKE[7:0] XC_CKE[15:8] XC_CKE[23:16] BQ_CKR[7:0] BQ_CKR[15:8] BQ_CKR[23:16] XC_CKR[7:0] XC_CKR[15:8] XC_CKR[23:16] XCRES XCCMP XCGO Doc ID 018937 Rev 2 STA381BWS BP2B BP2A BP1B ZMTH[2:0] CPFEN CPOK ABFAULT F3X_ MUTE NP_CRC RES STC_LNK BRC_EN BCAUTO BCRES BCCMP SRESET SHEN BP1A DCROK ...
Page 105
... R/W 0 R/W 1 R/W 2 R/W The STA381BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: ● 32.768 MHz for 32 kHz ● 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz ● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...
Page 106
... R/W 7 R/W The on-chip STA381BWS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting which directs the power output block to begin recovery), holds for period of time in the range of 0 ...
Page 107
... Serial data interface The STA381BWS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA381BWS always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12 ...
Page 108
... Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data 2 0000 24-bit data 0001 0 Left-justified 16 to 24-bit data 0010 0 Right-justified 24-bit data 0110 0 Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data Doc ID 018937 Rev 2 STA381BWS Interface format ...
Page 109
... Table 108. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA381BWS work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock which means that: ■ the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in ■ ...
Page 110
... Register description: Sound Terminal compatibility To avoid any audio side effects (like pop noise strongly recommended to soft-mute any audio streams flowing into the STA381BWS data path before the desynchronization event happens. At the same time any processing related to the I only after the serial audio interface and the internal PLL are synchronous again. ...
Page 111
... Configuration register D (addr 0x03 SME ZDE 0 0 7.4.1 DSP bypass Table 113. DSP bypass Bit R/W 2 R/W Setting the DSPB bit bypasses the EQ function of the STA381BWS. Register description: Sound Terminal compatibility D5 D4 CSZ3 CSZ2 0 1 RST Name 1 CSZ0 When OM[1,0] = 11, this register determines the 1 ...
Page 112
... Setting of 1 enables the automatic zero-detect mute 0 ZDE Setting of 0 disables the automatic zero-detect mute RST Name 0: Submix into left/right disabled 0 SME 1: Submix into left/right enabled D5 D4 Reserved PWMS 0 0 Doc ID 018937 Rev 2 STA381BWS Description Description Description Description AME NSBW Reserved Reserved 0 ...
Page 113
... RST 3 R/W The STA381BWS features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately this mode, which is still greater than the SNR of AM radio. ...
Page 114
... D5 D4 ECLE LDTE 0 1 RST Name 0 OCFG0 Selects the output configuration 0 OCFG1 Output configuration Binary 0 ° Binary 90° Binary 0° Binary 90° w/ C3BO 45° w/ C3BO 45° Doc ID 018937 Rev 2 STA381BWS BCLE IDE OCFG1 Description PBTL Enable YES D0 OCFG0 0 ...
Page 115
... STA381BWS Figure 31. OCFG = 00 (default value) Figure 32. OCFG = 01 Figure 33. OCFG = 10 Register description: Sound Terminal compatibility OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half Bridge Bridge Channel 2 Channel 2 Half Half Bridge Bridge OUT2B ...
Page 116
... Register description: Sound Terminal compatibility Figure 34. OCFG = 11 The STA381BWS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries ...
Page 117
... STA381BWS For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage: 2.0 channels, two full-bridges (OCFG = 00) ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ● FFX2B -> OUT2B ● FFX3A -> OUT3A ● FFX3B -> OUT3B ● ...
Page 118
... OUT1B OUT2A OUT2A OUT2A OUT2A OUT2A OUT2A OUT2B OUT2B OUT2B OUT2B OUT2B OUT2B OUT3A OUT3A OUT3A OUT3A OUT3A OUT3A OUT3B OUT3B OUT3B OUT3B OUT3B OUT3B OUT4A OUT4A OUT4A OUT4A OUT4A OUT4B OUT4B OUT4B OUT4B OUT4B Doc ID 018937 Rev 2 STA381BWS Figure 37. ...
Page 119
... STA381BWS 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ● FFX2B -> OUT2B ● FFX3A -> OUT3A ● FFX3B -> OUT3B ● EAPD -> OUT4A ● TWARN -> OUT4B ● FFX1A/1B configured as ternary ● FFX2A/2B configured as ternary ● ...
Page 120
... Binary output mode clock loss detection enable Name LDTE LRCLK double trigger protection enable Name ECLE Auto EAPD on clock loss Name 0: IC power-down low-power condition 1 PWDN 1: IC normal operation Doc ID 018937 Rev 2 STA381BWS Description 2 S data and automatically Description Description Description Description 2 C ...
Page 121
... STA381BWS 7.6.7 External amplifier power-down Table 130. External amplifier power-down Bit R/W 7 R/W The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10. ...
Page 122
... Channel 3 / line output volume The volume structure of the STA381BWS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -80 dB. 122/168 ...
Page 123
... STA381BWS As an example if CH3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB. The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “ ...
Page 124
... Description 44.1 kHz/88.2 kHz input fs 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz Description -order high-pass filter (channels 1 and STA381BWS D0 AMAME 0 ...
Page 125
... STA381BWS Table 138. Bass management crossover frequency XO[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.9 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 7.9.1 Tone control bypass Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2 ...
Page 126
... Perform EQ on channel x - normal operation Bypass EQ on channel x Normal volume operations Volume is bypassed FFX 3-state output - normal operation Binary output Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 Doc ID 018937 Rev 2 STA381BWS Mode Mode Mode ...
Page 127
... STA381BWS 7.9.6 Output mapping Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. . Table 144. Channel output mapping as a function of CxOM bits ...
Page 128
... EATHx[6:0 recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA381BWS possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain ...
Page 129
... STA381BWS automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register ...
Page 130
... Slow 0.0451 Doc ID 018937 Rev 2 STA381BWS RMS Outp ut Saturatio n Table 147. Limiter release rate as a function of LxR bits LxR[3:0] Release rate dB/ms 0000 0.5116 0001 0.1370 0010 0.0744 0011 0.0499 0100 0 ...
Page 131
... STA381BWS Anticlipping mode Table 148. Limiter attack threshold as a function of LxAT bits (AC mode) LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register description: Sound Terminal compatibility AC (dB relative to fs) -12 - ...
Page 132
... EATH1[5] EATH1[4] EATH1[ ERTH1[5] ERTH1[4] ERTH1[ Doc ID 018937 Rev 2 STA381BWS as a function of LxRT bits (DRC mode) DRC (db relative to volume + LxAT) -∞ -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB - ...
Page 133
... STA381BWS 7.11.7 Limiter 2 extended attack threshold (addr 0x34 EATHEN2 EATH2[ The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 To enable this feature, the EATHEN2 bit must be set to 1 7.11.8 Limiter 2 extended release threshold (addr 0x35 ERTHEN2 ERTH2[ The extended release threshold value is determined as follows: ...
Page 134
... C3B13 C3B12 C3B11 C3B5 C3B4 C3B3 C4B21 C4B20 C4B19 Doc ID 018937 Rev 2 STA381BWS C2B18 C2B17 C2B16 C2B10 C2B9 C2B8 C2B2 C2B1 C2B0 ...
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... Coefficients for user-defined EQ, mixing, scaling, bass management and STCompressor (see Section 4.2) are handled internally in the STA381BWS via RAM. Access to this RAM is available to the user via this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...
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... C address 0x1E address 0x1F address 0x20 address 0x21 address 0x22 address 0x23 address 0x24 address 0x25 register 0x16 address 0x17 address 0x18 address 0x19 address 0x26. Doc ID 018937 Rev 2 STA381BWS ...
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... When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example 10, 20, 35 decimal), and the STA381BWS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. Register description: Sound Terminal compatibility 2 C register 0x16 ...
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... Register description: Sound Terminal compatibility 7.12.18 User-defined EQ The STA381BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0 ...
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... STA381BWS link bit. By default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4. Table 152. RAM block for biquads, mixing, scaling and bass management Index (decimal … … ...
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... FAULT 1: normal operation D5 D4 Reserved Reserved 0 0 Doc ID 018937 Rev FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 Reserved Reserved Reserved Description Reserved Reserved Reserved STA381BWS D0 FDRC8 0 D0 FDRC0 0 D0 Reserved D0 Reserved 0 ...
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... D6 MDRCE Reserved 0 0 The extended configuration register provides access to B 7.16.1 Dual-band DRC The STA381BWS device provides a dual-band DRC (B data path, as depicted in 2 Figure 40. B DRC scheme L R The low-frequency information (LFE) is extracted from left and right channels, removing the high frequencies using a programmable Biquad filter, and then computing the difference with the original signal ...
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... HP 2 DRC are the same as those described in Post-scale value is applied as defined in coefficient RAM Post-scale value is applied with +48 dB offset with respect to the coefficient RAM value Doc ID 018937 Rev 2 STA381BWS the corresponding low-pass 0 2 Chapter 7.11 DRC output. ...
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... STA381BWS 7.16.3 Extended attack rate The attack rate shown in on both limiters. Table 155. Extended attack rate, limiter 1 XAR1 0 1 Table 156. Extended attack rate, limiter 2 XAR2 0 1 7.16.4 Extended BIQUAD selector Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1 ...
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... SVDW[ When volume is increased, use the default rate When volume is increased, use the rates defined by SVUP[4:0]. When volume is decreased, use the default rate When volume is decreased, use the rates defined by SVDW[4:0]. Doc ID 018937 Rev 2 STA381BWS SVUP[2] SVUP[1] SVUP[ ...
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... STA381BWS 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40 VRESEN VRESTG reserved reserved 0 0 Extra volume resolution allows fine volume tuning by steps of 0.125 dB. The feature is enabled when VRESEN=1, as depicted in volume in this case will be CxVol+CxVR (in dB), while the master volume will be MVOL+MVR (in dB) ...
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... D7 D6 Reserved Reserved default the STA381BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’). 146/168 VRESTG 0 Extra volume resolution disabled ...
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... STA381BWS The output PLL frequency formula is: where Fin is the input clock frequency from the pad. Table 164. PLL factors PLL parameter FRAC IDIV NDIV Table 165. PLL register 0x43 bits Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Table 166. PLL register 0x44 bits ...
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... Input oversampling selected by IR bits 0 BOOST32K ‘1’: Input oversampling is selected x3 RST Name BYPSTATE PLL bypass state PDSTATE PLL PD State OSCOK OSCI locked LOWCK Clock input frequency check D5 D4 reserved reserved NA NA Doc ID 018937 Rev 2 STA381BWS Description Description reserved GNDSH VCCSH OUTSH NA ...
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... STA381BWS To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected noted that register 0x47 is meaningful only after the EAPD bit is set to ‘1’ at least once ...
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... Biquads from have in the STA381BWS the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the implementation of high shelf filters that may require a coefficient dynamic greater in absolute value than 1. Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated Each Biquad has its independent setting according to the following table. ...
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... STA381BWS 13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output, therefore this procedure must be used only in case pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a power-down applied through the IIC interface ...
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... D5 D4 BPTIM[5] BPTIM[4] BPTIM[ Doc ID 018937 Rev 2 STA381BWS Fade out time Default time divided by 2 Default time divided by 4 Default time divided by 8 Default time divided by 16 Default time divided by 32 Default time divided by 64 Default time divided by 128 D3 ...
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... STA381BWS The STA381BWS implements a detection on the PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect DC levels in the PWM outputs noted that the checks are performed on logic level PWM (i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 I/Os). ...
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... Headphone/Line out configuration register (address 0x55 HPLN Reserved 0 0 154/168 Value_in_dB = 20*Log (Reg_value/(2 10 Equivalent input level (dB) Equivalent input level hysteresis (dB MUTE Reserved CPFEN Doc ID 018937 Rev 2 STA381BWS 16 *0.635)) -78 -84 -90 -96 -102 -108 -114 -114 CPOK ABFAULT DCROK NA NA ...
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... STA381BWS Table 174. Headphone/Line out configuration bits. Bit R/W 7 R/W 5 R Register description: Sound Terminal compatibility RST Name When F3X is connected to the internal HP/Line driver this bit selectS the gain of the F3X->analog out path. ‘0’: HP out. When the MVOL+Channel Vol is 0 dBFs, ...
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... F3X_MUTE ‘1’: Mute 0 F3X_ENA ‘1’: F3X enable Doc ID 018937 Rev Reserved Reserved Reserved F3X_MUTE Description Description STA381BWS D0 Reserved 0 D0 F3X_ENA 0 ...
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... STA381BWS 7.27 STCompressor 0x5A; 0x5B reserved LIM_BYP reserved reserved 0 0 Table 177. STCompressor Bit R/W 6 R/W 5 R R/W Table 178. STCompressor Bit R R/W 0 Register description: Sound Terminal compatibility TM configuration register (address D5 D4 STC_BYP STC_ENA reserved reserved ...
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... XCCKR[21] XCCKR[20] XCCKR[19 XCCKR[21] XCCKR[20] XCCKR[19 XCCMP XCGO BCAUTO Doc ID 018937 Rev 2 STA381BWS BQCKE[2] BQCKE[1] BQCKE[ BQCKE[10] BQCKE[9] BQCKE[ BQCKE[18] BQCKE[17] BQCKE[16 ...
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... MCU will handle this event. ● Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA381BWS, on each audio frame, and the reset event will be triggered in case of checksum mismatch. ● ...
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... RST Name ‘0’: normal operation 0 SRESET ‘1’: reset the device D5 D4 reserved reserved 0 0 RST Name 1 SMAP ‘1’:NEWMAP, ‘0’=STMAP Doc ID 018937 Rev 2 STA381BWS reserved SRESET reserved Description reserved reserved reserved ...
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... Applications 8.1 Application schemes The following figures illustrate typical application schemes for the STA381BWS. The line/headphone out can be fed either with an external analog source F3X output, allowing to have the audio content coming from the digital interface on both the power output and on the line/headphone out ...
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... Applications Figure 45. F3X (from SAI) source to line/headphone out application scheme 162/168 STA381BWS Doc ID 018937 Rev 2 STA381BWS ...
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... STA381BWS Figure 46. F3X auxiliary analog output 8.2 Headphone and 2 Vrms line out Figure 47. Headphone and line out block diagram STA381BWS Doc ID 018937 Rev 2 Applications 163/168 ...
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... BTL stereo mode. Please refer to the application note for all the other schematics for the recommended output configuration. Figure 48. Output configuration for stereo BTL mode in filterlight configuration 164/168 Gain=R2/R1*2 Figure 44 and Figure 45. Thanks to this latter option it is Doc ID 018937 Rev 2 STA381BWS Figure 47. The ...
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... STA381BWS 9 Package information Figure 49. VQFN48 ( 0.9 mm) package dimensions Doc ID 018937 Rev 2 Package information 165/168 ...
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... Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. 166/168 Doc ID 018937 Rev 2 STA381BWS ® ...
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... STA381BWS 10 Revision history Table 181. Document revision history Date 08-Jun-2011 28-Jun-2011 Revision 1 Initial release 2 Removed TQFP64 package option Doc ID 018937 Rev 2 Revision history Changes 167/168 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 168/168 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 018937 Rev 2 STA381BWS ...