sta381bws STMicroelectronics, sta381bws Datasheet - Page 61

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
Table 34.
To make the STA381BWS work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
■
■
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA381BWS will immediately mute the I
and it will freeze any active processing task.
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,
where N depends on the settings in
the PLL must be locked.
32 * fs
48 * fs
64 * fs
BICKI
Supported serial audio input formats for LSB-first (SAIFB = 1)
SAI [3:0]
1100
1110
0100
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
Doc ID 018937 Rev 2
SAIFB
Table 30
2
S PCM data out (provided to the processing block)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
Left/right-justified 16-bit data
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
2
2
2
2
2
2
2
S 15-bit data
S 23-bit data
S 20-bit data
S 18-bit data
S 24-bit data
S 20-bit data
S 18-bit data
2
2
S 16-bit data
S 16-bit data
Register description: New Map
Interface format
61/168