sta381bws STMicroelectronics, sta381bws Datasheet - Page 45

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
6.1
6.2
CLK register (addr 0x00)
Table 15.
STATUS register (addr 0x01)
Table 16.
1. Fault status is set to 1 once the power bridge goes to tri-state mode.
Bit
Bit
FAULT
7
6
5
4
1
0
7
6
5
4
0
NA
D7
D7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
CLK register
STATUS register
DRCCRC
NA
D6
D6
0
CLK_CFG[3:0]
RST
RST
0
0
0
0
0
EQCRC
NA
D5
D5
0
BADPWM
CLK_CFG[3:0]
DRCCRC
FAULT
EQCRC
I2SERR
Doc ID 018937 Rev 2
PLLUL
Name
Name
I2S
(1)
BADPWM
NA
D4
D4
0
Description
‘0’= the power bridge is in fault condition
‘1’= the power bridge is in normal condition
‘0’= normal operation
‘1’= CRC error on DRC BIQUADS
‘0’= normal operation
‘1’= CRC error on BIQUADS
‘0’= normal operation
‘1’= PWM outputs are invalid
‘0’= normal operation
‘1’= SAI interface error detected (see
Configuration register B (addr
‘0’= PLL is locked
‘1’= PLL is not locked
Description
0000: 44.1/48 kHz BITCLK = 64 Fs
0001: 32 kHz BITCLK = 64 Fs
0010: 96 kHz BITCLK = 64 Fs
0011: 48/44.1/32 kHz MCK = 256 Fs
others: clock configuration depends on IR/MCS bits
‘0’= SAI configured in I
‘1’= SAI configuration depends on CONFB register
status
Reserved
Reserved
NA
D3
D3
0
Register description: New Map
Reserved
Reserved
D2
D2
NA
0
2
S mode
0x12))
Reserved
I2SERR
NA
D1
D1
0
Section 6.14:
PLLUL
I2S
NA
D0
D0
0
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