sta381bws STMicroelectronics, sta381bws Datasheet - Page 87

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
6.27
PLL configuration registers (address 0x52; 0x53; 0x54; 0x55;
0x56; 0x57)
By default, the STA381BWS is able to configure the embedded PLL automatically
depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to
the user, a manual PLL configuration can be used (setting
The output PLL frequency formula is:
where Fin is the input clock frequency from the pad.
Table 81.
PLL_DPD
Reserved
Reserved
NA
D7
D7
D7
PLL_DITH[1:0]
D7
D7
D7
0
0
0
0
0
PLL parameter
FRAC
NDIV
PLL_FCT
PLL factors
IDIV
Reserved
Reserved
NA
D6
D6
D6
D6
D6
D6
0
0
0
0
0
PLL_DIRP PLL_PWD
PLL_STB
Reserved
NA
D5
D5
D5
D5
D5
D5
Fin
0
0
0
0
0
Doc ID 018937 Rev 2
×
PLL_STBB
⎛
⎝
-------------------------- -
(
Reserved
IDIV
(
YP
NA
NDIV
D4
D4
D4
D4
D4
D4
0
0
0
0
0
PLL_FRAC[15:8]
PLL_FRAC[7:0]
Min
+
0
0
5
1
)
BYPSTATE PDSTATE
PLL_BYP
)
+
PLL_NDIV[5:0]
NA
D3
D3
D3
D3
D3
D3
0
0
0
0
0
⎛
⎝
FRAC
---------------- -
65536
Register description: New Map
PLL_DIRP to ‘1’)
OSC_PD
⎞
⎠
D2
D2
D2
D2
D2
D2
NA
⎞
⎠
PLL_IDIV[3:0]
0
0
0
0
0
Reserved
OSCOK
65535
NA
D1
D1
D1
D1
D1
D1
0
0
0
0
0
Max
55
3
BOOST32
LOWCK
NA
D0
D0
D0
D0
D0
D0
K
0
0
0
0
0
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