sta381bws STMicroelectronics, sta381bws Datasheet - Page 148

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: Sound Terminal compatibility
7.20
148/168
Table 167. PLL register 0x45 bits
Table 168. PLL register 0x46 bits
Short-circuit protection mode registers SHOK (address 0x47)
The following power bridge pins short-circuit protections are implemented in the
STA381BWS:
●
●
●
The protection is enabled when reg. 0x4C bit 0 (SHEN) is set to ‘1’. The protection will check
the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched
on), and only if the test passes (no short) does the power bridge leave the tristate condition.
Register 0x47 (read-only registers) will give more information about the detected short type.
GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is
shorted to OUT2A.
Bit
Bit
reserved
5
4
3
2
0
3
2
1
0
NA
D7
OUTxx vs GNDx
OUTxx vs VCCx
OUT1B vs OUT2A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
reserved
NA
D6
RST
RST
0
0
0
0
0
reserved
NA
D5
BOOST32K
BYPSTATE
PLL_DIRP
PLL_PWD
PDSTATE
PLL_BYP
OSC_PD
Doc ID 018937 Rev 2
OSCOK
LOWCK
Name
Name
reserved
NA
D4
‘0’: PLL configuration is determined by MCS bits
‘1’: PLL configuration is determined by FRAC, IDIV
and NDIV
‘0’: PLL normal behavior
‘1’: PLL is in power-down mode
‘0’: sys clock is from PLL
‘1’: sys clock is from external pin (PLL is bypassed)
‘0’: Normal behavior
‘1’: Internal oscillator is in power down
‘0’: Input oversampling selected by IR bits
‘1’: Input oversampling is selected x3
PLL bypass state
PLL PD State
OSCI locked
Clock input frequency check
reserved
NA
D3
GNDSH
Description
Description
D2
NA
VCCSH
NA
D1
STA381BWS
OUTSH
NA
D0