sta381bws STMicroelectronics, sta381bws Datasheet - Page 91

no-image

sta381bws

Manufacturer Part Number
sta381bws
Description
Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA381BWS
Manufacturer:
ST
0
Part Number:
STA381BWS
Manufacturer:
ST
Quantity:
20 000
Part Number:
sta381bwsTR
Manufacturer:
ST
0
STA381BWS
6.30
6.30.1
6.30.2
Table 86.
In this case the user can decide, for each filter stage, the right coefficient range. Note that for
a given biquad the same range will be applied to left and right (channel 1 and channel 2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1)
range unchanged.
Miscellaneous registers (address 0x5C, 0x5D)
Rate power-down enable (RPDNEN) bit
In the STA381BWS, by default, the power-down pin and I
commands to perform the fadeout. This default can be changed so that the fadeout can be
started using the master volume. The RPDNEN bit, when set, activates this feature.
Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)
A fadeout procedure is started in the STA381BWS once the PWDN function is enabled, and
after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge
will be switched off immediately after the PWDN pin is tied to ground, without waiting for the
13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the
immediate power-down will generate a pop noise at the output, therefore this procedure
must be used only in case pop noise is not relevant in the application. Note that this feature
works only for hardware PWDN assertion and not for a power-down applied through the IIC
interface. Refer to
needed.
RPDNEN
LPDP
D7
D7
0
0
CEXT_Bx[1]
Coefficients extended range configuration
Reserved
0
0
1
1
LPD
D6
D6
1
1
Section 6.30.5
BRIDGOFF
LPDE
D5
D5
1
0
Doc ID 018937 Rev 2
if programming a different number of clock cycles is
PNDLSL[2]
Reserved
D4
D4
0
0
CEXT_Bx[0]
0
1
0
1
PNDLSL[1]
Reserved
D3
D3
0
1
Register description: New Map
PNDLSL[0]
CPWMEN
2
D2
D2
1
1
C power-down act on mute
Reserved
Reserved
Reserved
D1
D1
Range
0
0
[-1;1)
[-2;2)
[-4;4)
Reserved
SHEN
D0
D0
0
0
91/168

Related parts for sta381bws