fin210ac Fairchild Semiconductor, fin210ac Datasheet
fin210ac
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fin210ac Summary of contents
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... Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Description 10-bit 48MHz The FIN210AC µSerDes™ low-power serializer / Camera or LCD deserializer optimized for use in cell phone displays and camera paths. The device reduces a 10-bit data path to four wires. For camera applications, an additional master clock m68 & ...
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... VDDP GND E DP[8] DP[9] GND VDDS F DP[10] GND N/C VDDA G N/C PLL1 PLL0 GND 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Description 5 6 N/C CKREF /DIRO STROBE DP[4] 1 DP[5] 2 CKSO+ CKSO - DP[6] 3 VDDP ...
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... N/C DP[7] VDDP GND E DP[8] DP[9] GND VDDS F DP[10] N/C N/C VDDA G N/C N/C PWS1 PWS0 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Description 5 6 N/C CKREF STROBE /DIRO DP[4] 1 DP[5] 2 CKSO+ CKSO- DP[6] 3 VDDP 4 DSI+ DSI- ...
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... Non-Inverted 26ns Inverted 26ns Non-Inverted 52.1ns Non-Inverted 69.4ns Power-Down © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Function CKREF STROBE Slow Frequencies 5MHz to 15MHz ≤ CKREF (Up to 15MHz) 5MHz to 14.2MHz ≤ CKREF (Up to 14.2MHz) 5MHz to 15MHz ≤ CKREF / 2 (Up to 7.5MHz) 5MHz to 15MHz ≤ ...
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... Power-Down States When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode. ...
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... PLL Note Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end of the higher speed PLL range. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 6 www.fairchildsemi.com ...
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... XTRM GND /RES Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package) Deserializer Configuration: ~2 – 3ns output edge rates (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 FIN210AC Deserializer VDD VDDS/A VDDS ...
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... Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package) Serializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 FIN210AC Serializer VDD VDDP2 E4 F4 ...
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... Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales representative or contact Fairchild directly. For samples and questions, please contact: Interface@fairchildsemi.com. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 9 www.fairchildsemi.com ...
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... Absolute Maximum Ratings. Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Parameter Serial I/O Pins to GND All Pins Parameter 10 Min. Max. Unit -0.5V +4.6 -0.5 V +0.5 DD Continuous -65 ...
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... Power Supply Currents Symbol Parameter I V Power-Down Supply Current DD_PD DD Dynamic Serializer Power Supply I DD_SER1 Current Dynamic Deserializer Power Supply I DD_DES1 Current © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Test Conditions I =-2.0mA, S1=0,S0 =-0.4mA, S1=1,S0 =-1.0mA, S1=1,S0 =2.0mA, S1=0,S0 =0.4mA, S1=1,S0 ...
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... TCCD (6) Output Delay Phase Lock Loop (PLL) AC Electrical Characteristics t Serializer PLL Stabilization Time TPLLS0 t PLL Disable Time Loss of Clock TPLLD0 t PLL Power-Down Time TPLLD1 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Test Conditions DIRI=1, S1=0, S0=0, V =2.5V DD Test Conditions S1=0, S0 S1=1, S0=0 CKREF STRB S1=1, S0=1 ...
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... Deserializer Disable Time LOW to DPTri-State; DIRI=0, t DISDES DISDES DP Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid. t Serializer Disable Time LOW to CKP HIGH DISSER © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 (Continued) Test Conditions PWS1 t PDV = STRB CKREF 0 ...
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... Sketch A (Side or Front Sectional View) Component Rotation Dia A max Dia A Dim B Tape Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0 Min. ±0.1 ±0.1 ± ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 5. ...
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... Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 Package Description 42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch ...
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... Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 17 www.fairchildsemi.com ...