fin210ac Fairchild Semiconductor, fin210ac Datasheet - Page 5

• Manufacturer Part Number: fin210ac
• Description: ?serdes Fin210ac 10-bit Serializer / Deserializer Supporting Cameras And Small Displays Up To 48mhz
• Manufacturer: Fairchild Semiconductor

Table 3.
Slow Edge Rates
Medium Edge Rates
Fast Edge Rates
Power Down
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12)
Example: CKREF=26MHz
CKREF = Strobe 50% Duty Cycle
If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP
Table 4.
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The
power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all
internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode.
Table 5.
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
Signal Pins
STROBE
DP[1:10]
CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns
CKREF
/DIRO
PLL0
CKP
1
Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values)
CKREF = Strobe 50% Duty Cycle
Power-Down
Serializer
LVCMOS Output Edge Rates
~2 - 3ns (C
~7 - 8ns (C
;
~4 - 5ns (C
PLL Multiplier=1; Pwidth Multiplier=6
DIRI=1 (Serializer)
L
Inputs Disabled
L
Input Disabled
Input Disabled
L
= 8pF)
= 8pF)
PLL1
= 8pF)
0
HIGH
0
5
DIRI=0 (Deserializer)
Outputs High-Z
PWS0
Input Disabled
Input Disabled
/ENZ = 0
0
High-Z
1
Deserializer
S0
0
1
1
0
DIRI=0 (Deserializer)
Input Disabled
Input Disabled
Outputs Low
/ENZ = 1
PWS1
High
0
www.fairchildsemi.com
1
S1
1
1
0
0
(1)
(2)