tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 38

• Manufacturer Part Number: tmp19a43fd
• Description: 32-bit Risc Microprocessor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

x
x
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(7) The 3rd byte, which the target board receives from the controller, is a command. The code for the
(8) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the
(9) The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password.
(10) The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the
x I/O Interface mode
RAM Transfer command is 10H.
3rd byte. Before sending back the acknowledge response, the boot program checks for a receive
error. If there was a receive error, the boot program transmits x8H and returns to the state in which
it waits for a command again. In this case, the upper four bits of the acknowledge response are
undefined — they hold the same values as the upper four bits of the previously issued command.
When the SIO0 is configured for I/O Interface mode, the boot program does not check for a
receive error.
If the 3rd byte is equal to any of the command codes listed in Table 3.2, the boot program echoes it
back to the controller. When the RAM Transfer command was received, the boot program echoes
back a value of 10H and then branches to the RAM Transfer routine. Once this branch is taken, a
password check is done. Password checking is detailed in Section 3.3.11.
If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and
returns to the state in which it waits for a command again. In this case, the upper four bits of the
acknowledge response are undefined — they hold the same values as the upper four bits of the
previously issued command.
The 5th byte is compared to the contents of address 0x0000_03F4 in the flash memory; the 6th
byte is compared to the contents of address 0x0000_03F5 in the flash memory; likewise, the 16th
byte is compared to the contents of address 0x0000_03FF in the flash memory. If the password
checking fails, the RAM Transfer routine sets the password error flag.
checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the
two’s complement of the total sum. Transmit this checksum value from the controller to the target
board. The checksum calculation is described in details in Section 3.3.13.
The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O
Interface mode (clocked by the rising edge of SCLK0), writes 30H to the SC0BUF. Then, the
SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of
the 1st byte, the controller should send the SCLK clock to the target board after a certain idle
time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte,
which is from the target board to the controller, is 30H, then the controller should take it as a
go-ahead. The controller must then delivers the 3rd byte to the target board at a rate equal to
the desired baud rate. The boot program sets the RXE bit in the SC0MOD register to enable
reception before loading the SIO transmit buffer with 30H.
TMP19A43 (rev2.0)3-24
Flash Memory Operation
TMP19A43