tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 98

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tmp19a43fd

Manufacturer Part Number
tmp19a43fd
Description
32-bit Risc Microprocessor
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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SCK Output Mode/
OUTPUT DATA
5.9 Serial Channel Timing
Active-Low SCK
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
SCL Input Mod
SCLK period
SCLK Clock High width(input)
SCLK Clock Low width (input)
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
INPUT DATA
Input Mode
Active-High
I/O Interface modeÔ
SCLK
SCLK
RxD
TxD
In the table below, the letter x represents the fsys cycle period, which varies depending on the
programming of the clock gear function.
 SCLK input modeÔ
 SCLK output mode  ÔSIO0 to SIO2Õ
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
é
tSCY
TscH
TscL
tOSS
tOHS
tSRD
tHSR
tSCY
tOSS
tOHS
tSRD
tHSR
Sym
Sym
bol
bol
12x
6x
6x
2x-30
8x-15
30
2x+30
8x
4x-10
4x-10
45
0
TMP19A43 5-27
Õ
Õ
Min
VALID
Min
1
Equation
Equation
1
t
HSR
t
OHS
Max
Max
300
150
150
20
185
30
80
200
90
90
45
0
Min
Min
VALID
2
40 MHz
40 MHz
2
Max
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMP19A43
Unit
Unit
VALID
3
3

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