tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 57

• Manufacturer Part Number: tmp19a43fd
• Description: 32-bit Risc Microprocessor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Read
Read/reset
ID-Read
Automatic page
programming (note)
Automatic chip
erase
Auto
Block erase (note)
Protection bit
programming
Protection bit
erase
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
Command
sequence
Always set "0" to the address bits [1:0] in the entire bus cycle. (Setting values to bits [7:2] are undefined.)
Bus cycles are "bus write cycles" except for the second bus cycle of the Read command, the fourth bus cycle of
the Read/reset command, and the fifth bus cycle of the ID-Read command. Bus write cycles are executed by SW
commands. Use "Data" in the table for the rt register [7:0] of SW commands. The address [31:16] in each bus write
cycle should be the target flash memory address [31:16] of the command sequence. Use "Addr." in the table for the
address [15:0].
In executing the bus write cycles, the interval between each bus write cycle shall be 15 system clocks or more.
The "Sync command" must be executed immediately after completing each bus write cycle.
Execute the "Sync command" immediately following the "LW command" after the fourth bus write cycle of the ID-
Read command.
(4) List of Command Sequences
(5) Supplementary explanation
x RA:
x RD:
x IA:
x ID:
x PA:
x PD:
x BA:
x PBA: Protection bit address
After the fourth bus cycle, enter data in the order of the address for a page.
First bus
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
Addr.
cycle
0xXX
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
Data
0xF0
Read address
Read data
ID address
Program page address
Program data (32-bit data)
Block address
ID data
Table 3-7Flash Memory Access from the Internal CPU
Second bus
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
cycle
Addr.
Data
0x55
0x55
0x55
0x55
0x55
0x55
0x55
TMP19A43 (rev2.0)3-43
Third bus
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
0x55XX
Addr.
cycle
Data
0xA0
0x9A
0x6A
0xF0
0x90
0x80
0x80
Fig. 3-6
Fourth bus
0x55XX
0x55XX
0x55XX
0x55XX
cycle
Addr.
0xAA
0xAA
0xAA
0xAA
Data
0x00
PD0
PA
IA
RA
RD
Fifth bus
0xAAXX
0xAAXX
0xAAXX
0xAAXX
cycle
Addr.
0xXX
Data
0x55
0x55
0x55
0x55
PD1
PA
ID
Flash Memory Operation
RA
RD
Sixth bus
TMP19A43
0x55XX
0x55XX
0x55XX
cycle
Addr.
0x9A
0x6A
Data
0x10
0x30
PD2
BA
PA


Seventh bus
Addr.
cycle
Data
0x9A
0x6A
PBA
PBA
PD3
PA