atmega103 ATMEL Corporation, atmega103 Datasheet - Page 25

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Reset Sources
0945I–AVR–02/07
The ATmega103(L) has three sources of reset:
•
•
•
During reset, all I/O Registers except the MCU Status Register are then set to their initial
values and the program starts execution from address $0000. The instruction placed in
address $0000 must be a JMP (absolute jump) instruction to the reset handling routine.
If the program never enables an interrupt source, the Interrupt Vectors are not used and
regular program code can be placed at these locations. The circuit diagram in Figure 23
shows the reset logic. Table 5 defines the timing and electrical parameters of the reset
circuitry.
$0012
$0014
$0016
$0018
$001A
$001C
$001E
$0020
$0022
$0024
$0026
$0028
$002A
$002C
$002E
;
$0030
$0031
$0032
$0033
$0034
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
...
MAIN:
...
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
ldi
out
ldi
out
<instr>
...
POT
).
...
TIM2_COMP
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMP
TIM0_OVF
SPI_STC
UART_RXC
UART_DRE
UART_TXC
ADC
EE_RDY
ANA_COMP
r16, high(RAMEND); Main program start
SPH,r16
r16, low(RAMEND)
SPL,r16
xxx
; Timer2 Compare Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; UART RX Complete Handler
; UDR Empty Handler
; UART TX Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
ATmega103(L)
25