atmega103 ATMEL Corporation, atmega103 Datasheet - Page 79

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

0945I–AVR–02/07
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN
is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following falling edge of the ADC clock cycle. The actual sample-and-hold takes
place one ADC clock cycle after the start of the conversion. The result is ready and writ-
ten to the ADC Result Register after 13 cycles. The ADC needs two more clock cycles
before a new conversion can be started. If ADSC is set high in this period, the ADC will
start the new conversion immediately. For a summary of conversion times, see Table
26.
Figure 47. ADC Timing Diagram, First Conversion
Table 26. ADC Conversion Time
Figure 48. ADC Timing Diagram
Cycle number
ADC clock
ADEN
ADSC
Hold strobe
ADIF
ADCH
ADCL
Cycle number
ADC clock
ADSC
Hold strobe
ADIF
ADCH
ADCL
Condition
1st Conversion
Single Conversion
1
2
Dummy Conversion
1
2
12
Number
Sample
Cycle
3
13
14
1
4
14
15
5
Result Ready
16
6
Number)
(Cycle
17
7
26
13
One Conversion
18
8
19
9
20
Actual Conversion
Time (Cycles)
10
21
Conversion
22
11
Total
ATmega103(L)
28
15
23
12
24
13
25
14
26
MSB of result
LSB of result
Conversion
Time (µs)
15
140 - 560
75 - 300
27
Total
Next Conversion
MSB of result
LSB of result
1
28
Second
Conversion
2
1
79
2