atmega103 ATMEL Corporation, atmega103 Datasheet - Page 87

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Port A Schematics
Port B
0945I–AVR–02/07
pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 28. DDAn Effects on Port A Pins
Note:
Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)
Port B is an 8-bit bi-directional I/O port with internal pull-ups.
Three I/O memory address locations are allocated for Port B, one each for the Data
Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B
Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data
Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can
sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as
DDAn
0
0
1
1
n: 7,6...0, pin number
PORTAn
PAn
0
1
0
1
MOS
PULL-
UP
WP:
WD:
RL:
RP:
RD:
SRE:
A:
D:
W:
R:
n:
Output
Output
Input
Input
I/O
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
EXT. SRAM ENABLE
ADDRESS
DATA
WRITE
READ
0-7
Pull-up
Yes
No
No
No
Comment
Tri-state (high-Z)
PAn will source current if ext. pulled low.
Push-pull Zero Output
Push-pull One Output
RL
RP
ATmega103(L)
Q
Q
PORTAn
RESET
RESET
DDAn
WD
RD
WP
R
C
R
C
D
D
SRE
R
W
An
Dn
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