xr17v254 Exar Corporation, xr17v254 Datasheet - Page 11
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xr17v254
Manufacturer Part Number
xr17v254
Description
66mhz Pci Bus Quad Uart With Power Management Support
Manufacturer
Exar Corporation
Datasheet
1.XR17V254.pdf
(70 pages)
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REV. 1.0.0
N
The XR17V254 supports D0, D3
from the D3
state transitions of the V254.
D0 S
The XR17V254 must be placed in the D0 state before being used in a system. The D0 state represents two
states - D0 Uninitalized and D0 Active. Upon entering D0 from power up or transition from D3
be in the D0 Uninitialized state. Once initialized by the system software, the V254 will enter the D0 Active state.
In the D0 Active state, the V254 is fully functional and will respond to all PCI bus transactions as well as issue
interrupts (INTA#). The system software can program the V254 to enter the D3
D3
The V254 enters the D3
the V254 will not be fully functional. The V254 will respond only to PCI configuration space accesses, if a PCI
clock is provided and will not respond to PCI memory accesses nor will it issue interrupts. However, the V254
will continue to receive data and the automatic software and hardware flow control, if enabled, will continue to
function normally. While in the D3
enabled by setting PME_Enable bit, upon one of the following events:
The V254 also sets the PME_Status bit when such an event occurs, regardless of whether the PME_Enable bit
is set or not. The system software can reset the PME_Status bit by writing a ’1’ to it. When the system software
programs the V254 from D3
state and will retain all the values of its internal registers. The V254 will keep its PCI signal drivers disabled for
the duration of the D3
registers and functional state information) in the D3
Note: The V254 has a sleep mode which keeps the power consumption to a minimum (see Sleep Mode
description on
the V254 in sleep mode (via the software driver) in the Active D0 state anytime or specifically when the system
software commands the V254 to enter the D3
given in Sleep Mode section on
same section occurs. Upon re-starting, the oscillator may take a long time to settle. This time may be more
than 20ms which is the maximum wait time guaranteed by the system software before resuming normal PCI
bus transactions in the Active D0 state. Therefore, there may be data errors if the V254 is commanded to
transmit data before the oscillator is ready. It is recommended not to use sleep mode while in the D3
state for this reason.
1.2.1
OTE
A
O
HOT
DDRESS
■
■
FFSET
: RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-Clear.
TATE
RX pin of any of the channels goes LOW (START bit detected), or
Any of the delta bits of modem inputs (MSR register bits [3:0]) is set in any of the 4 channels (see
page
S
TATE
Power States and Power State Transitions of the V254
hot
49)
B
14:9
page
7:2
1:0
state. The following paragraphs describe these power states and
8
ITS
22). This is independent of the power state the V254 is in. The user can optionally place
hot
hot
RWR
RWR
T
RO
RO
YPE
to D0 Uninitialized state transition. The V254 saves the PME context (configuration
state when the system software programs the V254 from D0 to D3
hot
to D0, typically in response to the PME# signal, the V254 enters the D0 Active
page 22
hot
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
T
hot
ABLE
and D3
state, the V254 asserts the PME# (Power Management Event) signal, if
2: P
are satisfied, and re-starts when one of the events as described in the
cold
OWER
hot
power states and is capable of generating the PME# signal
state. The crystal oscillator shuts down when the conditions
M
hot
ANAGEMENT
11
state.
PME_Enable
D
PowerState
Reserved
Reserved
ESCRIPTION
R
EGISTERS
hot
state from the D0 state.
Figure 4
shows the power
hot
(
hot
HEX OR BINARY
XR17V254
R
, the V254 will
ESET
. In this state,
000000b
00000b
00b
0b
V
ALUE
hot
)