xr17v254 Exar Corporation, xr17v254 Datasheet - Page 38

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit [5]) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1]) when
the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit
empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely
empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the source of the
transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
F
4.6.3
4.6.4
IGURE
F
IGURE
15. T
16. T
(8XMODE
16X or 8X
Register)
Transmitter Operation in FIFO Mode
Auto RS485 Operation
(8XMODE Register)
Auto Software Flow Control
(Xoff1/2 and Xon1/2 Reg.
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
Clock
16X or 8X Clock
RANSMITTER
RANSMITTER
Data
Byte
O
PERATION IN NON
O
Transmit Shift Register (TSR)
Data Byte
Transmit
PERATION IN
Transmit
Register
Holding
(THR)
FIFO
Transmit Data Shift Register
-FIFO M
AND
(64-Byte)
Transmit
F
ODE
FIFO
(TSR)
LOW
38
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
THR Interrupt (ISR bit-1) falls
when becomes empty. FIFO
ODE
below Programmed Trigger
is Enabled by FCR bit-0=1
Level (TXTRG) and then
M
S
B
TXNOFIFO1
L
S
B
TXFIFO1
REV. 1.0.0