xr17v254 Exar Corporation, xr17v254 Datasheet - Page 69
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xr17v254
Manufacturer Part Number
xr17v254
Description
66mhz Pci Bus Quad Uart With Power Management Support
Manufacturer
Exar Corporation
Datasheet
1.XR17V254.pdf
(70 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr17v254IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr17v254IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.0
4.0 UART...................................................................................................................................................... 29
5.0 UART CONFIGURATION REGISTERS ................................................................................................ 40
ABSOLUTE MAXIMUM RATINGS ................................................................................. 58
ELECTRICAL CHARACTERISTICS............................................................................... 58
DC ELECTRICAL CHARACTERISTICS
4.1 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 29
4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION................................. 31
4.3 INFRARED MODE ............................................................................................................................................. 33
4.4 INTERNAL LOOPBACK.................................................................................................................................... 34
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING .......................................... 34
4.6 TRANSMITTER.................................................................................................................................................. 37
4.7 RECEIVER ......................................................................................................................................................... 39
5.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 40
5.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ............................................................................... 40
5.3 BAUD RATE GENERATOR DIVISORS (DLM, DLL AND DLD)....................................................................... 40
5.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 40
5.5 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. 42
5.6 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 43
5.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 45
5.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 47
5.9 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 48
5.10 MODEM STATUS REGISTER (MSR) - READ ONLY ..................................................................................... 49
5.11 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 50
5.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 52
5.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................... 52
5.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 53
5.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 55
5.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 55
5.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 55
5.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY .................................................................. 55
5.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 55
5.20 XCHAR REGISTER, READ ONLY .................................................................................................................. 56
T
F
T
F
F
F
T
T
F
F
F
F
T
T
T
T
T
T
T
ABLE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
4.6.1 TRANSMIT HOLDING REGISTER (THR)..................................................................................................................... 37
4.6.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 37
4.6.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 38
4.6.4 AUTO RS485 OPERATION .......................................................................................................................................... 38
4.7.1 RECEIVER OPERATION IN NON-FIFO MODE .......................................................................................................... 39
4.7.2 RECEIVER OPERATION WITH FIFO........................................................................................................................... 40
5.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 40
5.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 41
5.5.1 INTERRUPT GENERATION: ........................................................................................................................................ 42
5.5.2 INTERRUPT CLEARING: ............................................................................................................................................. 42
BIT FORMAT................................................................................................................................................... 28
11: T
12: T
13: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 35
14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
15: I
16: T
17: P
18: A
19: 16 S
20: S
21: UART RESET CONDITIONS ...................................................................................................................................... 57
11. B
12. A
13. I
14. I
15. T
16. T
17. R
18. R
NTERRUPT
RANSMIT AND
YPICAL DATA RATES WITH A
RANSMIT AND
ARITY
UTO
OFTWARE
NFRARED
NTERNAL
RANSMITTER
RANSMITTER
AUD
UTO
ECEIVER
ECEIVER
ELECTABLE
RS485 H
R
RTS/DTR
P
ATE
ROGRAMMING
L
T
S
F
O
O
OOP
RANSMIT
OURCE AND
LOW
G
PERATION IN NON
PERATION IN
R
ENERATOR
R
O
O
ALF
H
ECEIVE
ECEIVE
PERATION IN NON
PERATION IN
B
YSTERESIS
C
AND
ACK
-
ONTROL
DUPLEX
D
CTS/DSR F
................................................................................................................................................. 34
ATA
................................................................................................................................................. 46
D
FIFO T
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
P
............................................................................................................................................. 30
ATA
FIFO
RIORITY
E
D
F
24 MH
L
NCODING AND
UNCTIONS
IRECTION
FIFO
R
-FIFO M
EVELS
RIGGER
EGISTER IN
AND
-FIFO M
L
LOW
Z CRYSTAL OR EXTERNAL CLOCK AT
AND
EVEL
F
W
FOR
LOW
ODE
C
HEN
T
C
........................................................................................................................ 55
F
ONTROL
ABLE AND
ONTROL
LOW
..................................................................................................................... 43
ODE
3.3V
C
B
.................................................................................................................. 39
R
T
YTE FORMAT
ONTROL
ECEIVE
RIGGER
PRELIMINARY
C
............................................................................................................ 38
ONTROL
D
SIGNALLING
O
L
ELAY FROM
PERATION
II
EVEL
D
M
T
ATA
ABLE
ODE
M
, 16C550
S
D
ODE
ELECTION
......................................................................................... 40
-D
ECODING
...................................................................................... 32
T
IS
................................................................................... 38
................................................................. 58
RANSMIT
S
ELECTED
COMPATIBLE
.......................................................................... 33
.......................................................................... 45
16X S
HADED BITS ARE ENABLED BY
-
TO
-R
................................................................ 53
AMPLING
ECEIVE
.......................................................... 28
................................................. 30
................................................. 51
EFR B
XR17V254
IT
-4. ....... 36