xr17v254 Exar Corporation, xr17v254 Datasheet - Page 28

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2)
and 0x700 (channel 3).
The THR and RHR register address for channel 0 to channel 3 is shown in
for each channel 0 to 3 are located sequentially at address 0x000, 0x200, 0x400 and 0x600. Transmit data
byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register
when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus
operation can only write or read in bytes.
3.2
3.1.3
Data Bit-31
Write n+0 to n+3
Write n+4 to n+7
W
PCI Bus
RITE
B7 B6 B5 B4 B3 B2 B1 B0
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
Etc.
Transmit Data Byte n+3
TX FIFO
Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700
T
ABLE
CH0 0x000 Read RHR
CH2 0x400 Read RHR
CH3 0x600 Read RHR
CH3 0x600 Write THR
CH0 0x000 Write THR
CH1 0x200 Write THR
CH1 0x200 Read RHR
CH2 0x400 Write THR
11: T
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address
RANSMIT AND
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible)
FIFO Data n+3
FIFO Data n+7
B
YTE
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+2
3
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
0x0100, 0x0300, 0x0500 and 0x0700
D
ATA
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
FIFO Data n+2
FIFO Data n+6
R
B
EGISTER IN
YTE
28
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
B7 B6 B5 B4 B3 B2 B1 B0
2
Transmit Data Byte n+1
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
B
YTE FORMAT
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
FIFO Data n+1
FIFO Data n+5
B
Table 11
YTE
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
, 16C550
1
B7 B6 B5 B4 B3 B2 B1 B0
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
below. The THR and RHR
Transmit Data Byte n+0
COMPATIBLE
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
FIFO Data n+0
FIFO Data n+4
B
YTE
Data Bit-0
REV. 1.0.0
PCI Bus
0