xr17v254 Exar Corporation, xr17v254 Datasheet - Page 68

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
GENERAL DESCRIPTION ................................................................................................ 1
PIN DESCRIPTIONS ......................................................................................................... 3
FUNCTIONAL DESCRIPTION .......................................................................................... 7
1.0 XR17V254 INTERNAL REGISTERS........................................................................................................ 8
2.0 CRYSTAL OSCILLATOR / BUFFER ..................................................................................................... 25
3.0 TRANSMIT AND RECEIVE DATA ......................................................................................................... 26
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
PCI Local Bus Interface .............................................................................................................................................. 7
PCI Local Bus Configuration Space Registers ........................................................................................................... 7
Power Management Registers ................................................................................................................................... 7
EEPROM Interface ..................................................................................................................................................... 7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... 8
1.2 POWER MANAGEMENT REGISTERS ............................................................................................................. 10
D0 State.................................................................................................................................................................... 11
D3hot State............................................................................................................................................................... 11
D3cold State ............................................................................................................................................................. 12
1.3 SPECIAL READ/WRITE REGISTER TO STORE USER INFORMATION ........................................................ 12
1.4 EEPROM INTERFACE....................................................................................................................................... 13
1.5 DEVICE INTERNAL REGISTER SETS ............................................................................................................. 13
1.6 DEVICE CONFIGURATION REGISTERS ......................................................................................................... 15
TIMER OPERATION ................................................................................................................................................ 19
3.1 FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT ...................................................................... 26
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-
F
F
F
T
T
F
T
T
T
T
T
F
T
T
F
T
F
F
F
F
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
ABLE
ABLE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
1.2.1 POWER STATES AND POWER STATE TRANSITIONS OF THE V254 ..................................................................... 11
1.6.1 THE GLOBAL INTERRUPT REGISTER....................................................................................................................... 16
1.6.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-
1.6.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 21
1.6.4 REGA [15:8] (DEFAULT 0X00) RESERVED................................................................................................................ 21
1.6.5 RESET [23:16] (DEFAULT 0X00)................................................................................................................................. 21
1.6.6 SLEEP [31:24] (DEFAULT 0X00) ................................................................................................................................. 22
1.6.7 DEVICE IDENTIFICATION AND REVISION ................................................................................................................. 22
1.6.8 REGB REGISTER ......................................................................................................................................................... 23
1.6.9 MULTI-PURPOSE INPUTS AND OUTPUTS ................................................................................................................ 23
1.6.10 MPIO REGISTER ........................................................................................................................................................ 23
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700.......................................... 27
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, AND 0X780 ................................. 27
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700 ................................................................ 28
1: PCI L
2: P
3: S
4: EEPROM A
5: XR17V254 UART
6: D
7: D
8: UART C
9: UART C
10: TIMER CONTROL R
1. B
2. P
3. T
4. P
5. T
6. T
7. T
8. I
9. M
10. T
00)................................................................................................................................................................................... 18
.................................................................................................................................................... 1
OWER
PECIAL
EVICE
EVICE
NTERRUPT
HE
HE
IMER
IMER
LOCK
IN
OWER
ULTIPURPOSE INPUT
YPICAL OSCILLATOR CONNECTIONS
............................................................................................................................................... 1
O
XR17V254 R
OCAL
G
UT OF THE
/C
LOBAL
M
C
C
O
D
HANNEL
HANNEL
R
S
ONFIGURATION
ONFIGURATION
OUNTER CIRCUIT
UTPUT IN
ANAGEMENT
IAGRAM OF THE
EAD
TATE
B
DDRESS
O
US
I
/W
UTPUT
NTERRUPT
................................................................................................................................ 2
T
C
[3:0] I
[3:0] I
RITE
RANSITIONS OF THE
D
ONFIGURATION
AND
O
EGISTER
EVICE
D
NE
(
R
ACTIVE
R
EFINITIONS
/
NTERRUPT
NTERRUPT
EGISTERS
OUTPUT INTERNAL CIRCUIT
D
-S
EGISTER
EGISTERS
R
R
.................................................................................................................................................. 2
EVICE
............................................................................................................................................... 18
XR17V254 ............................................................................................................................... 1
R
HOT AND
EGISTERS SHOWN IN
EGISTERS SHOWN IN
EGISTER
S
LOW)
ETS
C
TABLE OF CONTENTS
S
..................................................................................................................................... 12
ONFIGURATION
..................................................................................................................................... 8
.................................................................................................................................... 13
S
C
.................................................................................................................................... 19
................................................................................................................................... 10
PACE
OURCE
R
LEARING
, INT0, INT1, INT2
IN
E
XR17V254............................................................................................................ 12
............................................................................................................................. 26
-
TRIGGERABLE
O
R
NE
EGISTERS
E
PRELIMINARY
-S
NCODING
................................................................................................................... 17
HOT AND
BYTE
DWORD
R
........................................................................................................... 24
EGISTERS
......................................................................................................... 9
M
ALIGNMENT
..................................................................................................... 17
I
ODES
R
AND
ALIGNMENT
E
-
TRIGGERABLE
INT3 .................................................................................. 17
........................................................................................... 14
.......................................................................................... 20
................................................................................... 15
............................................................................... 16
M
ODES
............................................................ 21
REV. 1.0.0