wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet
wm8593seft-v
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wm8593seft-v Summary of contents
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... Set Top Boxes http://www.wolfsonmicro.com/enews/ WM8593 DAC: 100dB SNR typical (‘A’ weighted @ 48kHz) DAC: -87dB THD typical ADC: 96dB SNR typical (‘A’ weighted @ 48kHz) ADC: -80dB THD typical I2S, LJ, RJ, DSP Production Data, April 2008, Rev 4.0 Copyright ©2008 Wolfson Microelectronics plc ...
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WM8593 BLOCK DIAGRAM Control Interface Stereo ADC ADC Input Mux VIN1L VIN1R VIN2L VIN2R VIN3L VIN3R VIN4L VIN4R VIN5L VIN5R VIN6L VIN6R VIN7L VIN7R VIN8L VIN8R W WM8593 w Audio Interface Mux Volume Control Matrix Channel Digital Volume Control Filters ...
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Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 PIN CONFIGURATION...........................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................8 SUPPLY CURRENT CONSUMPTION ...................................................................8 ELECTRICAL CHARACTERISTICS ......................................................................9 TERMINOLOGY .......................................................................................................... 11 MASTER CLOCK TIMING ........................................................................................... 12 /RESET TIMING .......................................................................................................... ...
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... WM8593 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8593SEFT/V -40°C to +85°C WM8593SEFT/RV -40°C to +85°C Note: Reel quantity = 750 w PACKAGE MOISTURE SENSITIVITY 64-lead TQFP (Pb-free) 64-lead TQFP (Pb-free, tape and reel) Pre-Production PACKAGE BODY LEVEL TEMPERATURE o MSL3 260 C o MSL3 ...
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Production Data PIN DESCRIPTION PIN NAME 1 DIO1 Digital Input/Output 2 MCLK2 Digital Input/Output 3 LRCLK2 Digital Input/Output 4 BCLK2 Digital Input/Output 5 DIO2 Digital Input/Output 6 MCLK3 Digital Input/Output 7 LRCLK3 Digital Input/Output 8 BCLK3 Digital Input/Output 9 DIO3 ...
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WM8593 PIN NAME 49 ADCREFP Analogue Output 50 ADCVMID Analogue Output 51 ADCREFN Analogue Input 52 DACREFP Analogue Input 53 DACVMID Analogue Output 54 DACREFN Analogue Input 55 AVDD1 56 AGND1 57 MODE 58 SDOUT Digital Output 59 /CS 60 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8593 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital power supply Analogue power supply Analogue power supply Ground DGND/AGND1/ Operating temperature range Notes: 1. Digital supply (DVDD) must never be more than 0.3V greater than AVDD1 in normal operation. 2. Digital ground (DGND) ...
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Production Data ELECTRICAL CHARACTERISTICS Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, T PARAMETER Digital logic levels Input low level Input high level Output low level Output high level Digital input leakage current Digital input capacitance Analogue Reference Levels ADC Midrail Voltage ...
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WM8593 Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, T PARAMETER DAC Performance 1,5 Signal to Noise Ratio 2,5 Dynamic Range 3,5 Total Harmonic Distortion 4,5 Channel Separation Channel Level Matching Channel Phase Deviation Power supply rejection ratio ADC Performance 1,5 Signal ...
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Production Data Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, T PARAMETER Headphone Amplifier Output signal level (0dB) 1,5 Signal to Noise Ratio Total Harmonic Distortion 4,5 Channel Separation Power Supply Rejection Ratio Digital Volume Control ADC minimum digital volume ADC maximum ...
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WM8593 Notes: 1. All minimum and maximum values are subject to change. 2. This resistance is selectable using VMID_SEL[1:0] – see Figure 54 for full details. 3. See p100 for details of extended input impedance configuration. MASTER CLOCK TIMING Figure ...
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Production Data DIGITAL AUDIO INTERFACE TIMING – SLAVE MODE BCLKx (Input) LRCLKx (Output) DIOx (Input) DIOx (Output) Figure 3 Slave Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T ...
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WM8593 DIGITAL AUDIO INTERFACE TIMING – MASTER MODE Figure 4 Master Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T 24-bit data, unless otherwise stated. PARAMETER Audio Data Input ...
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Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T 24-bit data, unless otherwise stated. PARAMETER Program ...
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WM8593 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 6 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T 24-bit data, unless otherwise stated. PARAMETER Program Register ...
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Production Data POWER ON RESET (POR) Figure 1 Power Supply Timing Requirements Test Conditions DVDD = 3.3V, AVDD1 = 3.3V, AVDD2 = 9V DGND = AGND1 = AGND2 = 0V, T AVDD1 = DVDD = 3.63V, AVDD1 max max AVDD2 ...
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WM8593 DEVICE DESCRIPTION INTRODUCTION The WM8593 is a high performance multi-channel audio CODEC with 2Vrms line level inputs and outputs and flexible analogue and digital input / output switching. The device comprises a 24-bit stereo ADC, two 24-bit stereo DACs ...
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Production Data CONTROL INTERFACE Control of the WM8593 is achieved by a 2-wire SM-bus-compliant or 3-wire SPI compliant serial interface with readback. Software interface mode is selected using the MODE pin as shown in Table 8 below: MODE (PIN 57) ...
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WM8593 AUTO-INCREMENT REGISTER WRITE It is possible to write to multiple consecutive registers using the auto-increment feature. When AUTO_INC is set, the register write protocol follows the method shown in Figure 8. As with normal register writes, the controller indicates ...
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Production Data 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL INTERFACE MODE REGISTER WRITE SDIN is used for the program data, SCLK is used to clock in the program data and /CS is use to latch in the program data. SDIN is sampled ...
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WM8593 DEVICE ID AND REVISION Reading from register R0 returns the device ID. Reading from register R1 returns the device revision number. REGISTER ADDRESS R0 DEVICE_ID 00h R1 REVISION 01h Table 10 Device ID and Revision Number DIGITAL AUDIO DATA ...
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Production Data I2S MODE mode, the MSB of input data is sampled on the second rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the first falling edge ...
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WM8593 RIGHT JUSTIFIED (RJ) MODE In RJ mode the LSB of input data is sampled on the rising edge of bit clock preceding a left/right clock transition. The LSB of output data changes on the falling edge of bit clock ...
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Production Data DSP MODE B In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge following a left/right clock rising edge. Channel 1 right data then follows. The MSB ...
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WM8593 REGISTER ADDRESS R7 DAC2_CTRL1 07h R13 ADC_CTRL1 0Dh Table 11 Audio Interface Control w BIT LABEL DEFAULT 5 DAC1_LRP 0 DAC1 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted 1:0 DAC2_ 10 DAC2 Audio Interface Format ...
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Production Data DIGITAL AUDIO INTERFACE Digital audio data is transferred to and from the WM8593 via the digital audio interface. The DACs have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate in both master ...
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WM8593 REGISTER ADDRESS R8 DAC1_CTRL2 08h R9 DAC2_CTRL3 09h R14 ADC_CTRL2 0Eh R15 ADC_CTRL3 0Fh Table 12 ADC Master Mode Control w BIT LABEL DEFAULT 2:0 DAC2_ 000 DAC MCLK:LRCLK Ratio SR[2:0] 000 = Auto detect 001 = 128fs 010 ...
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Production Data SLAVE MODE In slave mode, the master clock to left/right clock ratio can be auto-detected or set manually by register write. REGISTER ADDRESS R3 DAC1_CTRL2 03h R8 DAC2_CTRL2 08h R14 ADC_CTRL2 0Eh Table 13 Slave Mode MCLK to ...
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WM8593 DIGITAL AUDIO DATA SAMPLING RATES In a typical digital audio system there is one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s ...
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Production Data DAC FEATURES The WM8593 includes two 24-bit DACs with independent clocks and independent data inputs. The DACs include digital volume control with zero cross and soft mute, de-emphasis support, and the capability to select the output channels to ...
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WM8593 REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 17 DAC Digital Volume Control SOFTMUTE A soft mute can be applied to DAC1 and DAC2 independently. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 18 DAC Softmute Control ...
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Production Data DIGITAL MONOMIX CONTROL Each DAC can be independently set to output a range of mono and stereo options. Each DAC output channel can output left channel data, right channel data or a mix of left and right channel ...
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WM8593 ADC FEATURES The WM8593 features a stereo 24-bit sigma-delta ADC, digital volume control with zero cross, a selectable high pass filter to remove DC offsets, and support for both master and slave clocking modes. REGISTER ADDRESS R13 ADC_CTRL1 0Dh ...
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Production Data CHANNEL SWAP AND INVERSION The WM8593 ADC input channels can be inverted and swapped in a number of ways to provide maximum flexibility of input path to the ADC. The default configuration provides stereo output data with the ...
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WM8593 ANALOGUE ROUTING CONTROL The WM8593 has a number of analogue paths, allowing flexible routing of a number of analogue input signals and DAC output signals at levels up to 2Vrms. The analogue paths include volume control with zero cross, ...
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Production Data REGISTER ADDRESS R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h ...
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WM8593 VOLUME RAMP Analogue volume can be adjusted by step change or by soft ramp. The ramp rate is dependent upon the sampling rate. The sampling rate upon which the volume ramp rate is based can be selected between the ...
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Production Data Note: When ATTACK_BYPASS=1 or DECAY_BYPASS= recommended that the zero cross function for the PGA is used to eliminate click noise when changing volume settings. REGISTER ADDRESS R25 PGA_CTRL1 19h R27 ADD_CTRL1 1Bh R36 PGA_CTRL3 24h Table ...
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WM8593 ANALOGUE MUTE CONTROL The analogue PGAs can be muted independently and are muted by default. Alternatively, all mute bits can be set using a master mute bit, MUTE_ALL. Setting one of these mute bits is equivalent to setting the ...
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Production Data INPUT SELECTOR CONTROL Each left channel input PGA can select between all left channel analogue inputs, and both left and right DAC inputs. Each right channel input PGA can select between all right channel analogue inputs, and both ...
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WM8593 REGISTER ADDRESS R28 INPUT_CTRL1 1Ch R29 INPUT_CTRL2 1Dh R28 INPUT_CTRL1 1Ch R29 INPUT_CTRL2 1Dh R31 INPUT_CTRL4 1Fh Table 30 PGA Input Select Control w BIT LABEL DEFAULT 3:0 PGA1L_ 0000 Left Input PGA Source Selection IN_ 0000 = No ...
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Production Data ADC INPUT SELECTOR CONTROL The ADC input switch can be configured to allow any combination of two inputs to be input to the ADC. Each input switch channel can be controlled independently. The input switch also includes PGAs ...
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WM8593 REGISTER ADDRESS R31 INPUT_CTRL4 1Fh Table 31 ADC Input Switch Control OUTPUT SELECTOR CONTROL Any analogue PGA channel can be routed to any analogue output. Care should be taken to ensure that each analogue output is routed to only ...
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Production Data REGISTER ADDRESS R32 OUTPUT_ CTRL1 20h R33 OUTPUT_ CTRL2 21h R34 OUTPUT_ CTRL3 22h Table 32 Output Selection w BIT LABEL DEFAULT 2:0 VOUT1L_ 000 Output Mux Selection SEL[2:0] 000 = PGA1L 5:3 VOUT1R_ 001 001 = PGA1R ...
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WM8593 DIGITAL ROUTING CONTROL The WM8593 includes a highly flexible digital routing multiplexer, allowing several independent systems to be directly connected to the WM8593 without the need for glue logic. The WM8593 consists of five digital audio ‘ports’, each with ...
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Production Data DIGITAL AUDIO PORT PIN CONFIGURATION The MCLK1 and DIO1 pins are defined individually as an input or an output using MCLK1_SEL[2:0] and DIO1_SEL[2:0] respectively. outputs together using WORDCLK1_SEL[2:0]. REGISTER ADDRESS R37 AIF_MUX1 25h Table 33 Digital Audio Port ...
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WM8593 The MCLK2 and DIO2 pins are defined individually as an input or an output using MCLK2_SEL[2:0] and DIO2_SEL[2:0] respectively. outputs together using WORDCLK2_SEL[2:0]. REGISTER ADDRESS R38 AIF_MUX2 26h Table 34 Digital Audio Port 2 Pin Configuration w The BCLK2 ...
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Production Data The MCLK3 and DIO3 pins are defined individually as an input or an output using MCLK3_SEL[2:0] and DIO3_SEL[2:0] respectively. outputs together using WORDCLK3_SEL[2:0]. REGISTER ADDRESS R39 AIF_MUX3 27h Table 35 Digital Audio Port 3 Pin Configuration w The ...
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WM8593 The MCLK4 and DIO4 pins are defined individually as an input or an output using MCLK4_SEL[2:0] and DIO4_SEL[2:0] respectively. outputs together using WORDCLK4_SEL[2:0]. REGISTER ADDRESS R40 AIF_MUX4 28h Table 36 Digital Audio Port 4 Pin Configuration w The BCLK4 ...
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Production Data The MCLK5 and DIO5 pins are defined individually as an input or an output using MCLK5_SEL[2:0] and DIO5_SEL[2:0] respectively. outputs together using WORDCLK5_SEL[2:0]. REGISTER ADDRESS R41 AIF_MUX5 29h Table 37 Digital Audio Port 5 Pin Configuration w The ...
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WM8593 ADC AUDIO INTERFACE CLOCK CONFIGURATION The WM8593 ADC has an independent audio interface which can be configured to select the required signals from any of the digital audio ports. The audio interface is not restricted to take each signal ...
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Production Data REGISTER ADDRESS R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh Table 39 DAC1 and DAC2 Audio Interface Clock Configuration w BIT LABEL DEFAULT 3:1 DAC1 001 DAC MCLK ...
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WM8593 UPDATE FUNCTION To prevent clock contention issues during setup of the digital audio interface mux, an update system has been implemented. This allows the registers to be configured as required and the update to be applied with the last ...
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Production Data Figure 25 Clock Switching Example If CLK_A in the previous example is not running the logic that controls switching between clocks will not function. In this case possible to force an update on any individual digital ...
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WM8593 USING GPIO PINS AS ADDITIONAL DATA PINS There are two GPIO pins, GPIO1 and GPIO2, which can be used as additional pins to connect to external devices. GPIO1 is controlled by GPIO1_SEL[2:0] and GPIO2 by GPIO2_SEL[2:0]. REGISTER ADDRESS R45 ...
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Production Data JACK DETECT When using the WM8593 with headphones, a jack detect function is available using the GPIO pins. The jack detect function is controlled using GPIO1_APP and GPIO2_APP. The polarity of the jack detect signal can be inverted ...
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WM8593 POP AND CLICK PERFORMANCE The WM8593 includes a number of features designed to minimise pops and clicks in various phases of operation including power up, power down, changing analogue paths and starting/stopping clocks. In order to ensure optimum performance, ...
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Production Data POWERDOWN SEQUENCE Power supplies can now be safely removed from the WM8593 if desired. w Mute all PGAs: • MUTE_ALL=1 Set up biases for power down mode: • FAST_EN=1 ...
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WM8593 Table 45 describes the various bias control bits for power up/down control: REGISTER ADDRESS R35 BIAS 23h Table 45 Bias Control GLOBAL ENABLE CONTROL The WM8593 includes a number of enable and disable mechanisms to allow the device to ...
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Production Data EMERGENCY POWER DOWN In the event of sudden power failure in a system, or any other emergency condition, the /PWDN pin may be used to power the device down from any state in a controlled manner. This may ...
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Production Data R0 (0h) – Software Reset / Device ID Register (DEVICE_ID) Bit # 15 14 Read Write Default 1 0 Bit # 7 6 Read Write Default 1 0 Function Device ID DEVICEID[15:0] A read of this register will ...
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WM8593 R2 (02h) – DAC Control Register 1 (DAC1_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC1_ DAC1_ZCEN DEEMPH Write Default 1 0 Function DAC1_FMT[1:0] DAC1 Audio Interface Format ...
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Production Data R3 (03h) – DAC1 Control Register 2 (DAC1_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function DAC1_SR[2:0] DAC1 MCLK:LRCLK ...
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WM8593 R5 (05h) – DAC1L Digital Volume Control Register (DAC1L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function DAC1L_VOL[7:0] DAC1L Digital Volume 0000 0000 = ...
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Production Data R7 (07h) – DAC2 Control Register 1 (DAC2_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC2_ DAC2_ZCEN DEEMPH Write Default 1 0 Function DAC2 Audio Interface Format ...
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WM8593 R8 (08h) – DAC2 Control Register 2 (DAC2_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function DAC2 MCLK:LRCLK Ratio DAC2_SR[2:0] ...
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Production Data R10 (0Ah) – DAC2L Digital Volume Control Register (DAC2L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function DAC2 Digital Volume DAC2L_VOL[7:0] 0000 0000 ...
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WM8593 R12 (0Ch) – Device Enable Register (ENABLE) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function GLOBAL_EN Device Global Enable 0 ...
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Production Data ADC_LRSWAP ADC Left/Right Swap 0 = Normal 1 = Swap left channel data into right channel and vice-versa ADCR_INV ADCL and ADCR Output Signal Inversion ADCL_INV 0 = Output not inverted 1 = Output inverted ADC Data Output ...
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WM8593 R15 (0Fh) – ADC Control Register 3 (ADC_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function ADC Master Mode Select ...
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Production Data R17 (11h) – Right ADC Digital Volume Control Register (ADCR_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function Right ADC Digital Volume ADCR_VOL[7:0] ...
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WM8593 R19 (13h) – PGA1L Volume Control Register (PGA1L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 0 0 R20 (14h) – PGA1R Volume Control Register (PGA1R_VOL) Bit ...
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Production Data R23 (17h) – PGA3L Volume Control Register (PGA3L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 0 0 R24 (18h) – PGA3R Volume Control Register (PGA3R_VOL) ...
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WM8593 R25 (19h) – PGA Control Register 1 (PGA_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read PGA3R_ZC PGA3L_ZC Write Default 1 1 Function DECAY_BYPASS PGA Gain Decay Mode 0 ...
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Production Data R26 (1Ah) – PGA Control Register 2 (PGA_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read JD_PGA1L_ PGA3R_ MUTE MUTE Write Default 0 1 Function Master PGA Mute ...
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WM8593 R27 (1Bh) – Additional Control Register 1 (ADD_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 Write N/A Default 0 1 Function GPIO1 Application Select GPIO1_APP 0 = ...
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Production Data R28 (1Ch) – Input Control Register 1 (INPUT_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read PGA1R_IN_SEL[3:0] Write Default 0 0 R29 (1Dh) – Input Control Register 2 ...
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WM8593 R30 (1Eh) – Input Control Register 3 (INPUT_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADCR_SEL[3:0] Write Default 1 0 Function ADCL_SEL[3:0] ADC Input Select ADCR_SEL[3:0] 0000 = ...
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Production Data R31 (1Fh) – Input Control Register 4 (INPUT_CTRL4) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADCR_AMP_ ADCL_AMP_ EN EN Write Default 0 0 Function Input PGA Enable ...
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WM8593 R32 (20h) – Output Control Register 1 (OUTPUT_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VOUT2L_SEL[1:0] Write Default 1 0 R33 (21h) – Output Control Register 2 (OUTPUT_CTRL2) ...
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Production Data R34 (22h) – Output Control Register 3 (OUTPUT_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VOUT1L_EN APE_B Write Default 0 1 Function Output Amplifier Tristate Control VOUT1L_TRI ...
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WM8593 R35 (23h) – Bias Control Register (BIAS) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VMID_SEL[1:0] Write Default 0 0 Function POBCTRL Bias Source for Output Amplifiers 0 = ...
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Production Data R36 (24h) – PGA Control Register 3 (PGA_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function PGA_FORCE PGA Ramp ...
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WM8593 R37 (25h) – Audio Interface MUX Configuration Register 1 (AIF_MUX1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DIO1_ WORDCLK1_SEL[2:0] SEL[0] Write Default 0 0 Function Force Port 1 ...
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Production Data R38 (26h) – Audio Interface MUX Configuration Register 2 (AIF_MUX2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DIO2_ WORDCLK2_SEL[2:0] SEL[0] Write Default 1 0 Function Force Port ...
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WM8593 R39 (27h) – Audio Interface MUX Configuration Register 3 (AIF_MUX3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DIO3_ WORDCLK3_SEL[2:0] SEL[0] Write Default 0 0 Function Force Port 3 ...
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Production Data R40 (28h) – Audio Interface MUX Configuration Register 4 (AIF_MUX4) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DIO4_ WORDCLK4_SEL[2:0] SEL[0] Write Default 1 0 Function Force Port ...
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WM8593 R41 (29h) – Audio Interface MUX Configuration Register 5 (AIF_MUX5) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DIO5_ WORDCLK5_SEL[2:0] SEL[0] Write Default 0 1 Function Force Port 5 ...
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Production Data R42 (2Ah) – Audio Interface MUX Configuration Register 6 (AIF_MUX6) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC1DIN_ DAC1WORDCLK_SEL[2:0] SEL[0] Write Default 1 0 Function Force DAC1 ...
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WM8593 R43 (2Bh) – Audio Interface MUX Configuration Register 7 (AIF_MUX7) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC2DIN_ DAC2WORDCLK_SEL[2:0] SEL[0] Write Default 1 0 Function Force DAC2 Clocks ...
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Production Data R44 (2Ch) – Audio Interface MUX Configuration Register 8 (AIF_MUX8) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 ADCWORDCLK_SEL[2:0] Write N/A Default 0 1 Function ADC_FORCE Force ...
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WM8593 R45 (2Dh) – Audio Interface MUX Configuration Register 9 (AIF_MUX9) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function GPIO1_SEL[2:0] GPIO1 ...
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Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter ± 0.05dB Passband Passband Ripple Stopband Stopband Attenuation Group Delay DAC Filter – 32kHz to 96kHz ± 0.1dB Passband Passband Ripple Stopband Stopband attenuation f > 0.546fs Group Delay DAC ...
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WM8593 DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 66 DAC Digital Filter Frequency Response – 44.1, 48 and 96KHz 0 -20 -40 -60 -80 -100 0 0.1 0.2 0.3 0.4 ...
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Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 70 De-Emphasis Frequency Response (32kHz) Figure 72 De-Emphasis Frequency Response (44.1kHz - Frequency ...
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WM8593 ADC FILTER RESPONSES Magnitude (dB 0.00 0.25 0.50 -20 -40 -60 -80 -100 -120 -140 Frequency Figure 76 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8593 has a selectable digital high ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Notes: 1. AGND and DGND should ideally share a continuous ground plane. Where this is not possible recommended that AGND and DGND are connected as close to the WM8593 as possible. ...
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WM8593 RECOMMENDED ANALOGUE LOW PASS FILTER Figure 79 Recommended Analogue Low Pass Filter (shown for VOUT1L/R) Note: See WAN0176 for AC coupling capacitor selection information. An external single pole RC filter is recommended (see Figure 79) if the device is ...
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Production Data EXAMPLE CONFIGURATION FOR JACK DETECT The WM8593 contains a jack detect function as described on page 57. In order to use this function necessary to connect the required GPIO pin to the headphone connector to detect ...
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WM8593 PACKAGE DIMENSIONS FT: 64 PIN TQFP ( 1.0 mm ccc C -C- SEATING PLANE Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 0.95 1.00 ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...