wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 39
wm8593seft-v
Manufacturer Part Number
wm8593seft-v
Description
24-bit 192khz 2vrms Multi-channel Codec
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8593SEFT-V.pdf
(103 pages)
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Production Data
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Note: When ATTACK_BYPASS=1 or DECAY_BYPASS=1, it is recommended that the zero cross
function for the PGA is used to eliminate click noise when changing volume settings.
Table 28 Analogue Volume Ramp Control
PGA_CTRL1
ADD_CTRL1
PGA_CTRL3
REGISTER
ADDRESS
R25
R27
1Bh
R36
19h
24h
BIT
6:4
3:1
10
0
1
0
PGA_UPD
ATTACK_
DECAY_
BYPASS
BYPASS
SEL[2:0]
FORCE
LABEL
SR[2:0]
PGA_
PGA_
PGA_
DEFAULT
001
000
0
0
0
0
PGA Gain Decay Mode
0 = PGA gain will ramp down
1 = PGA gain will step down
PGA Gain Attack Mode
0 = PGA gain will ramp up
1 = PGA gain will step up
Sample Rate for PGA
000 = 32kHz
001 = 44.1kHz
010 = 48kHz
011 = 88.2kHz
100 = 96kHz
101 = 176.4kHz
11X = 192kHz
See Table 27 for further information on PGA
sample rate versus volume ramp rate.
PGA Ramp Control Clock Source Mux
Force Update
0 = Wait until clocks are safe before
switching PGA clock source
1 = Force PGA clock source to change
immediately
PGA Ramp Control Clock Source
000 = LRCLK1
001 = LRCLK2
010 = LRCLK3
011 = LRCLK4
100 = LRCLK5
101 = DACLRCLK1 (when DAC1 is being
used in master mode)
110 = DACLRCLK2 (when DAC2 is being
used in master mode)
111 = ADCLRCLK (when ADC is being used
in master mode)
PGA Ramp Control Clock Source Mux
Update
0 = Do not update PGA clock source
1 = Update clock source
DESCRIPTION
PD Rev 4.0 April 2008
WM8593
39
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