wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 76
wm8593seft-v
Manufacturer Part Number
wm8593seft-v
Description
24-bit 192khz 2vrms Multi-channel Codec
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8593SEFT-V.pdf
(103 pages)
- Current page: 76 of 103
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WM8593
R25 (19h) – PGA Control Register 1 (PGA_CTRL1)
Figure 46 R25 – PGA Control Register 1
w
Default
Default
Write
Write
Read
Read
Bit #
Bit #
ATTACK_BYPASS
DECAY_BYPASS
PGA1R_ZC
PGA2R_ZC
PGA3R_ZC
PGA1L_ZC
PGA2L_ZC
PGA3L_ZC
Function
PGA3R_ZC
N/A
15
0
7
0
1
PGA3L_ZC
PGA Gain Decay Mode
0 = PGA gain will ramp down
1 = PGA gain will step down
PGA Gain Attack Mode
0 = PGA gain will ramp up
1 = PGA gain will step up
PGA Gain Zero Cross Enable
0 = PGA gain updates occur immediately
1 = PGA gain updates occur on zero cross
Zero cross must be disabled to use gain ramp
N/A
14
0
0
6
1
PGA2R_ZC
N/A
13
0
0
5
1
PGA2L_ZC
N/A
12
0
0
4
1
Description
PGA1R_ZC
N/A
11
0
3
0
1
N/A = Not Applicable (no function implemented)
PGA1L_ZC
N/A
10
0
0
2
1
ATTACK_
BYPASS
N/A
PD Rev 4.0 April 2008
9
0
0
1
0
Production Data
DECAY_
BYPASS
N/A
8
0
0
0
0
76
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