wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 91

• Manufacturer Part Number: wm8593seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
R42 (2Ah) – Audio Interface MUX Configuration Register 6 (AIF_MUX6)
Figure 61 R42 – Audio Interface MUX Configuration Register 6
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Default
Default
DAC1MCLK_SEL[2:0]
Write
Write
Read
Read
Bit #
Bit #
DAC1DIN_SEL[2:0]
DAC1WORDCLK_
DAC1_FORCE
DAC1_UPD
Function
SEL[2:0]
DAC1DIN_
SEL[0]
N/A
15
0
7
0
1
Force DAC1 Clocks to Change
0 = Wait until clocks are safe before switching between clock sources
1 = Force clock sources to change immediately
See Table 41 for details of use.
DAC1MCLK Select
000 = Use MCLK1
001 = Use MCLK2
010 = Use MCLK3
011 = Use MCLK4
100 = Use MCLK5
101 to 111 = Reserved
DAC1BCLK and DAC1LRCLK Select
000 = Use BCLK1 and LRCLK1
001 = Use BCLK2 and LRCLK2
010 = Use BCLK3 and LRCLK3
011 = Use BCLK4 and LRCLK4
100 = Use BCLK5 and LRCLK5
101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)
110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)
111 = Use ADCBCLK and ADCBCLK (when ADC is master mode)
DAC1DIN Select
000 = Use DIO1
001 = Use DIO2
010 = Use DIO3
011 = Use DIO4
100 = Use DIO5
101 = Use GPIO1
110 = Use GPIO2
111 = Use ADCDOUT
DAC1 Clock Update
0 = Latch corresponding DAC1 clock settings into Register Map but do not update
1 = Latch corresponding DAC1 clock settings into Register Map and update all simultaneously
N/A
14
0
0
6
0
DAC1WORDCLK_SEL[2:0]
N/A
13
0
0
5
0
N/A
12
0
0
4
1
Description
N/A
11
0
3
0
0
DAC1MCLK_SEL[2:0]
N/A = Not Applicable (no function implemented)
DAC1_UPD
10
0
2
0
DAC1DIN_SEL[2:1]
9
0
1
1
PD Rev 4.0 April 2008
WM8593
FORCE
DAC1_
8
0
0
0
91