wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 87

• Manufacturer Part Number: wm8593seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
R38 (26h) – Audio Interface MUX Configuration Register 2 (AIF_MUX2)
Figure 57 R38 – Audio Interface MUX Configuration Register 2
w
Default
Default
WORDCLK2_SEL[2:0]
Write
Write
Read
Read
Bit #
Bit #
MCLK2_SEL[2:0]
PORT2_FORCE
DIO2_SEL[2:0]
PORT2_UPD
Function
SEL[0]
DIO2_
N/A
15
0
7
0
1
Force Port 2 Clocks to Change
0 = Wait until clocks are safe before switching between clock sources
1 = Force clock sources to change immediately
See Table 41 for details of use.
MCLK2 Pin Function Select
000 = Output MCLK1
001 = Input to WM8593
010 = Output MCLK3
011 = Output MCLK4
100 = Output MCLK5
101 to 111 = Reserved
BCLK2 and LRCLK2 Pins Function Select
000 = Output BCLK1 and LRCLK1
001 = Inputs to WM8593
010 = Output BCLK3 and LRCLK3
011 = Output BCLK4 and LRCLK4
100 = Output BCLK5 and LRCLK5
101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)
110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)
111 = Output ADCBCLK and ADCBCLK (when ADC is master mode)
DIO2 Pin Function Select
000 = Output DIO1
001 = Input to WM8593
010 = Output DIO3
011 = Output DIO4
100 = Output DIO5
101 = Output GPIO1
110 = Output GPIO2
111 = Output ADC Data Output
Port 2 Update
0 = Latch corresponding Port 2 settings into Register Map but do not update
1 = Latch corresponding Port 2 settings into Register Map and update all simultaneously
N/A
14
0
0
6
0
WORDCLK2_SEL[2:0]
N/A
13
0
0
5
0
N/A
12
0
0
4
1
Description
N/A
11
0
3
0
0
N/A = Not Applicable (no function implemented)
MCLK2_SEL[2:0]
PORT2_UPD
10
0
2
0
9
0
1
1
DIO2_SEL[2:1]
PD Rev 4.0 April 2008
WM8593
PORT2_
FORCE
8
0
0
0
87