wm8593seft-v Wolfson Microelectronics plc, wm8593seft-v Datasheet - Page 85

• Manufacturer Part Number: wm8593seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
R36 (24h) – PGA Control Register 3 (PGA_CTRL3)
Figure 55 R36 – PGA Control Register 3
w
Default
Default
Write
Write
Read
Read
Bit #
Bit #
PGA_SEL[2:0]
PGA_FORCE
PGA_UPD
Function
N/A
N/A
15
0
7
0
0
0
PGA Ramp Control Clock Source Mux Force Update
0 = Wait until clocks are safe before switching PGA clock source
1 = Force PGA clock source to change immediately
See page 39 for details of use.
PGA Ramp Control Clock Source
000 = LRCLK1
001 = LRCLK2
010 = LRCLK3
011 = LRCLK4
100 = LRCLK5
101 = DAC1LRCLK (when DAC1 is being used in master mode)
110 = DAC2LRCLK (when DAC2 is being used in master mode)
111 = ADCLRCLK (when ADC is being used in master mode)
PGA Ramp Control Clock Source Mux Update
0 = Do not update PGA clock source
1 = Update clock source
N/A
N/A
14
0
0
6
0
0
N/A
N/A
13
0
0
5
0
0
N/A
N/A
12
0
0
4
0
0
Description
N/A
11
0
3
0
0
N/A = Not Applicable (no function implemented)
PGA_SEL[2:0]
PGA_UPD
10
0
2
0
N/A
9
0
0
1
1
PD Rev 4.0 April 2008
WM8593
FORCE
PGA_
N/A
8
0
0
0
0
85