m24lr16e-r STMicroelectronics, m24lr16e-r Datasheet - Page 13

• Manufacturer Part Number: m24lr16e-r
• Description: 16 Kbit Eeprom With Password Protection, Dual Interface & Energy Harvesting 400 Khz I²c Bus & Iso 15693 Rf Protocol At 13.56 Mhz
• Manufacturer: STMicroelectronics

M24LR16E
1
Description
The M24LR16E-R device is a dual-interface, electrically erasable programmable memory
(EEPROM). It features an I
also a contactless memory powered by the received carrier electromagnetic wave. The
M24LR16E-R is organized as 2048 × 8 bits in the I
15693 and ISO 18000-3 mode 1 RF mode.
The M24LR16E-R also features an energy harvesting analog output, as well as a user-
configurable digital output pin toggling during either RF write in progress or RF busy mode.
Figure 1.
I
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR16E-R is accessed via the
13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the
received signal amplitude modulation (ASK: amplitude shift keying). When connected to an
antenna, the operating power is derived from the RF energy and no external power supply is
required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
Logic diagram
Table
2
C interface and can be operated from a V
Doc ID 018932 Rev 7
2), terminated by an acknowledge bit.
2
C protocol, with all memory operations synchronized
2
C mode and as 512 × 32 bits in the ISO
CC
power supply. It is
Description
th
13/143
2
bit
C