m24lr16e-r STMicroelectronics, m24lr16e-r Datasheet - Page 33

• Manufacturer Part Number: m24lr16e-r
• Description: 16 Kbit Eeprom With Password Protection, Dual Interface & Energy Harvesting 400 Khz I²c Bus & Iso 15693 Rf Protocol At 13.56 Mhz
• Manufacturer: STMicroelectronics

M24LR16E
5.5.1
5.5.2
5.6
I²C timeout on Start condition
I²C communication with the M24LR16E-R starts with a valid Start condition, followed by a
device select code.
If the delay between the Start condition and the following rising edge of the Serial Clock
(SCL) that samples the most significant of the Device Select exceeds the t
(see
until the next valid Start condition.
Figure 7.
I²C timeout on clock period
During data transfer on the I²C bus, the serial clock high pulse width High (
clock pulse width Low (
logic block is reset and any further incoming data transfer is ignored until the next valid Start
condition.
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
“Address” (E2,1,1). To address the memory array, the 4-bit device type identifier is 1010b.
Refer to
The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 2
SCL
SDA
Table
Table
(on Serial Data (SDA), most significant bit first).
123), the I²C logic block is reset and further incoming data transfer is ignored
I²C timeout on Start condition
condition
2.
Start
t
CLCH
) exceeds the maximum value specified in
Doc ID 018932 Rev 7
t
START_OUT
I
2
Table
C device operation
START_OUT
t
CHCL
123, the I²C
) or serial
MS19779V1
time
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