lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 14

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-9 illustrates the
DCS Block diagram.
Figure 2-9. DCS Block Diagram
Figure 2-10 shows timing waveforms for one of the DCS operating modes. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-10. DCS Waveforms
Clock Boosting
There are programmable delays available in the clock signal paths in the PFU, PIC and EBR blocks. These allow
setup and clock-to-output times to be traded to meet critical timing without slowing the system clock. If this feature
is enabled then the design tool automatically uses these delays to improve timing performance.
Global Set/Reset
There is a global set/reset (GSR) network on the device that is distributed to all FFs, PLLs, DLLs and other blocks
on the device. This GSR network can operate in two modes:
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the
input clock signal, while the feedback divider is used to multiply the input clock signal.
a) asynchronous - no clock is required to get into or out of the reset state.
b) synchronous - The global GSR net is synchronized to a user selected clock. In this mode it continues to be
asynchronous to get into the reset state, but is synchronous to get out of the reset state. This allows all reg-
isters on the device to become operational in the same clock period. The synchronous GSR goes out of
reset in two cycles from the clock edge where the setup time of the FF was met (not from the GSR being
released).
SEL
CLK0
DCSOUT
CLK1
CLK0
CLK1
SEL
DCS
2-10
DCSOUT
LatticeSC/M Family Data Sheet
Architecture