lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 61

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

LatticeSC/M Internal Timing Parameters
Lattice Semiconductor
PFU Logic Mode Timing
t
t
t
t
t
t
t
t
t
t
PFU Memory Mode Timing
t
t
t
t
t
t
t
PIC Timing
PIO Input/Output Buffer Timing
t
t
t
t
t
t
t
t
t
t
t
LUT4_PFU
LUT5_PFU
LSR_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
LE2Q_PFU
LD2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
LE2Q_PIO
LD2Q_PIO
Parameter
CTOF_DEL
MTOOFX_DEL LUT5 delay (inputs to output)
LSR_DEL
M_SET
M_HLD
DIN_SET
DIN_HLD
REG_DEL
LTCH_DEL
TLTCH_DEL
CLKTOF_DEL
DIN_SET
DIN_HLD
WAD_SET
WAD_HLD
WE_SET
WE_HLD
IN_DEL
DOPADI_DEL
DIN_SET
DIN_HLD
CK_DEL
CE_SET
CE_HLD
LSR_SET
LSR_HLD
CK_DEL
DIN_DEL
Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%
Symbol
LUT4 delay (A to D inputs to F output)
Set/Reset to output (asynchronous)
Clock to Mux (M0,M1) input setup
time
Clock to Mux (M0,M1) input hold time -0.041
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, D-type register
configuration
Clock to Q delay latch configuration
D to Q throughput delay when latch is
enabled
Clock to Output
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay(LVCMOS25)
Output Buffer Delay(LVCMOS25)
Input Register Setup Time (Data
Before Clock)
Input Register Hold Time (Data after
Clock)
Output Register Clock to Output
Delay
Input Register Clock Enable Setup
Time
Input Register Clock Enable Hold
Time
Set/Reset Setup Time
Set/Reset Hold Time
Input Register Clock to Q delay latch
configuration
Input Register D to Q throughput
delay when latch is enabled
Description
3-17
1
-0.028
-0.024
-0.176
-0.156
-0.267
-0.151
0.113
0.072
0.075
0.110
0.014
0.078
0.057
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
DC and Switching Characteristics
0.045
0.152
0.378
0.224
0.294
0.300
0.575
0.578
2.712
0.513
0.000
0.129
0.335
0.578
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeSC/M Family Data Sheet
-0.046
-0.032
-0.026
-0.196
-0.175
-0.306
-0.159
0.131
0.083
0.084
0.124
0.019
0.086
0.060
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
0.050
0.172
0.426
0.252
0.331
0.338
0.649
0.661
3.027
0.571
0.000
0.145
0.372
0.647
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.052
-0.035
-0.027
-0.215
-0.194
-0.345
-0.169
0.148
0.094
0.094
0.138
0.024
0.094
0.063
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
0.054
0.192
0.474
0.279
0.367
0.376
0.724
0.744
3.395
0.639
0.000
0.161
0.410
0.717
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns