lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 16

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
There is a Digital Control (DCNTL) bus available from the DLL block. This Digital Control bus is available to the
delay lines in the PIC blocks in the adjacent banks. The UDDCNTL signal allows the user to latch the current value
on the digital control bus.
Figure 2-12 shows the DLL block diagram of the DLL inputs and outputs. The output of the phase frequency detec-
tor controls an arithmetic logic unit (ALU) to add or subtract one delay tap. The digital output of this ALU is used to
control the delay value of the delay chain and this digital code is transmitted via the DCNTL bus.
The sysCLOCK DLL can be configured at power-up, then, if desired, reconfigured dynamically through the Serial
Memory Interface bus which interfaces with the on-chip Microprocessor Interface (MPI) bus. In addition, users can
drive the SMI interface from routing if desired.
The user can configure the DLL for many common functions such as clock injection match and single delay cell.
Lattice provides primitives in its design for time reference delay (DDR memory) and clock injection delay removal.
Figure 2-12. DLL Diagram
PLL/DLL Cascading
The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allow-
able combinations are as follows:
DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency
synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applica-
tions to utilize the unique benefits of both DLL and PLLs.
When cascading the DLL to the PLL, the DLL can be used to drive the PLL to create fine phase shifts of an input
clock signal. Figure 2-13 shows a shift of all outputs for CLKOP and CLKOS out in time.
• PLL to PLL
• PLL to DLL
• DLL to DLL
• DLL to PLL
ALUHOLD
UDDCNTL
RSTN
CLKFB
CLKI
PFD
ALU
2-12
Chain
Delay
Phase Adj
Phase Adj
DCNTL
Gen
LatticeSC/M Family Data Sheet
Duty50
Duty50
CLKOP
CLKOS
LOCK
DCNTL
Architecture