lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 57

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
LatticeSC/M External Switching Characteristics
General I/O Pin Parameters (using Primary Clock without PLL)
t
t
t
t
t
f
f
t
General I/O Pin Parameters (using Primary Clock with PLL)
t
t
t
General I/O Pin Parameters (using Edge Clock without PLL)
t
t
t
t
t
t
General I/O Pin Parameters (using Latch FF without PLL)
t
t
t
t
1. No PLL delay tuning (clock injection removal mode, system clock feedback).
2. Using LVCMOS25 12mA I/O. Timing adders for other supported I/O technologies are specified in the LatticeSC Family Timing Adders table.
3. Complete Timing Parameters for a user design are incorporated when running ispLEVER. This is a sampling of the key timing parameters.
CO
SU
H
SU_IDLY
H_IDLY
MAX_PFU
MAX_IO
GC_SKEW
CO
SU
H
CO
SU
H
SU_IDLY
H_IDLY
EC_SKEW
SU
H
SU_IDLY
H_IDLY
Parameter
Timing specs are for non-AIL applications.
Global Clock Input to Output - PIO Output Reg-
ister
Global Clock Input Setup - PIO Input Register
without fixed input delay
Global Clock Input Hold - PIO Input Register
without fixed input delay
Global Clock Input Setup - PIO Input Register
with input delay
Global Clock Input Hold - PIO Input Register
with input delay
Global Clock frequency of PFU register
Global Clock frequency of I/O register
Global Clock skew
Global Clock Input to Output - PIO Output Reg-
ister
Global Clock Input Setup - PIO Input Register
without fixed input delay
Global Clock Input Hold - PIO Input Register
without fixed input delay
Edge Clock Input to Output - PIO Output Regis-
ter
Edge Clock Input Setup - PIO Input Register
without fixed input delay
Edge Clock Input Hold - PIO Input Register
Edge Clock Input Setup - PIO Input Register
with input delay
Edge Clock Input Hold - PIO Input Register with
input delay
Edge Clock skew
Latch FF, Input Setup - PIO Input Register with-
out fixed input delay
Latch FF, Input Hold - PIO Input Register without
fixed input delay
Latch FF, Input Setup - PIO Input Register with
input delay
Latch FF, Input Hold - PIO Input Register with
input delay
Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%
Description
3-13
2
1, 2
2
-0.66
-0.17
-0.07
-0.08
-0.34
-0.14
-0.30
Min.
2.83
1.73
0.86
2.25
0.80
2.38
0.49
0.81
0.58
0.70
—
—
—
—
2
-7
Max.
1000
5.74
4.81
4.77
700
89
28
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
3
LatticeSC/M Family Data Sheet
-0.66
-0.17
-0.07
-0.08
-0.34
-0.14
-0.30
Min.
2.83
1.95
1.03
2.25
0.93
2.38
0.58
0.97
0.68
0.68
—
—
—
—
-6
Max.
1000
6.11
5.08
5.04
700
103
32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.66
-0.17
-0.07
-0.08
-0.34
-0.14
-0.30
Min.
2.83
2.16
1.20
2.25
1.04
2.38
0.66
1.12
0.77
0.77
—
—
—
—
-5
Max.
1000
6.49
5.37
5.33
700
116
36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns