lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 72

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
sysCONFIG MPI Port
LatticeSC/M sysCONFIG Port Timing (Continued)
t
t
t
t
t
t
t
t
f
sysCONFIG Asynchronous Peripheral Configuration Mode
t
t
t
t
t
t
t
sysCONFIG Slave Serial Configuration Mode
t
t
t
t
f
t
sysCONFIG Slave Parallel Configuration Mode
t
t
t
t
t
t
f
MPICTRL_SET
MPIADR_SET
MPIDAT_SET
MPIDPAR_SET
MPI_HLD
MPICTRL_DEL
MPIDAT_DEL
MPIDPAR_DEL
MPI_CLK_FRQ
WRAP
SAP
RDYAP
BAP
WR2AP
DENAP
DAP
SSS
HSS
CHSS
CLSS
CSS
DSS
S1SP
H1SP
S2SP
H2SP
CHSP
CL
CSP
Parameter
Parameter
MPI Control (MPCSTRBN, MPCWRN,
MPCCLK, etc.) to MPCCLK Setup Time
MPI Address to MPCCLK Setup Time
MPI Write Data to MPCCLK Setup Time
MPI Write Parity Data to MPCCLK Setup
Time
All Hold Times
MPCCLK to MPI Control (MPCTA, MPC-
TEA, MPCRETRY)
MPCCLK to MPI Data
MPCCLK to MPI Parity Data
MPCCLK Frequency
WRN, CS0N and CS1 Pulse Width
D[7:0] Setup Time
RDY Delay
RDY Low
Earliest WRN After RDY Goes High
RDN to D[7:0] Enable/Disable
CCLK to DOUT
DIN Setup Time
DIN Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
CS0N, CS1, WRN Setup Time
CS0N, CS1, WRN Hold Time
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
Description
Over Recommended Operating Conditions
Description
3-28
Min.
4.9
3.9
4.9
3.9
—
—
—
—
0
-7
Max.
100
5.6
5.6
4.9
—
—
—
—
—
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
Min.
5.2
4.2
4.2
5.2
—
—
—
—
0
-6
Min.
3.75
3.75
3.75
3.75
1.5
5.2
5.2
5.2
Max.
—
—
—
—
—
—
5
1
0
0
0
0
6.7
6.7
5.7
83
—
—
—
—
—
Min.
5.5
4.5
5.5
4.5
—
—
—
—
0
Max.
150
150
7.5
7.5
7.5
—
—
—
—
—
—
—
—
—
—
—
-5
8
8
-
-
Max.
8.7
8.7
7.7
66
—
—
—
—
—
periods
CCLK
Units
MHz
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns