lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 23

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-20. Input Register Block
PURESPEED
I/O Buffer)
(from
DI
1. UPDATE, Set and Reset not shown for clarity
2. Adaptive input logic is only available in selected PIO
3. By four shift modes utilize DDR/shift register block from paired PIO.
4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to
disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used
to disable any/all input signals to save power.
Delay
Block
1
Latch
Adaptive
CLKENABLE
Optional
Logic
Input
2
2-19
• DDR
• DDR + half clock
• DDR + shift x1
• DDR + shift x2
• DDR + shift x4
• Shift x1
• Shift x2
• Shift x4
DDR/Shift Register Block
SDR Register/Latch Block
D-Type/
3
Latch
CLKDISABLE
3
LatticeSC/M Family Data Sheet
IPOS0
IPOS1
INEG0
INEG1
LCLKIN (ECLK/SCLK)
HCLKIN (ECLK/SCLK)
DCNTL[0:8]
(From DLL)
INDD
INCK
INFF
LOCK
RUNAIL
Routing
To
Architecture