lfsc3ga15e-7f900c Lattice Semiconductor Corp., lfsc3ga15e-7f900c Datasheet - Page 22

• Manufacturer Part Number: lfsc3ga15e-7f900c
• Description: Latticesc/m Fpga Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
Adaptive Input Logic (AIL) Overview
The Adaptive Input Logic (AIL) provides the ability of the input logic to dynamically find a solution by monitoring
multiple samples of the input data. The input data signal from the input buffer is run through a delay chain. Data,
transitions, jitter, noise are all contained inside of the delay chain. The AIL will then search the delay chain for a
clean sampling point for data. Once found the AIL will monitor and walk with the data dynamically. This novel
approach of using a delay chain to create multiple copies of the data provides a lower power solution than over-
sampling data with a higher speed clock. Figure 2-19 provides a high level view of the AIL methodology.
Figure 2-19. LatticeSC AIL Delay of Input Data Waveform
Input Data Signal
Delay Chain
AIL Acquisition Window
The AIL slides the acquisition window through the delay chain searching for stable data based solely on data tran-
sitions. A specific training pattern is not required to perform this bit alignment, simply data transitions. The size of
the acquisition window is user-selectable allowing the AIL to operate over the full range of the PURESPEED I/O
range. Based on dynamic user control the AIL can either continuously adjust the window location based on data
edge detection or it can be locked to a specific delay.
The AIL operates on single data and double data rate interfaces and is available on most FPGA input pins on the
LatticeSC device and all buffer types. The AIL block is low power using only 0.003 mW/MHz typical (6 mW @ 2
7
Gbps) for PRBS 2
data. Multiple AIL inputs can be used to create a bus with a FPGA circuit to realign the bus to a
common clock cycle. The FPGA circuit to realign the bus is required and is provided by Lattice as a reference
design.
For more information on the LatticeSC AIL please refer to the LatticeSC AIL User’s Guide.
Input DDR/Shift Block
The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the
high-speed clock and the associated transfer to the low-speed clock domain. It functions as a gearbox allowing
high-speed incoming data to be passed into the FPGA fabric. Each PIO supports DDR and x2 shift functions. If
desired PIOs A and B or C and D can be combined to form x4 shift functions. The PIOs A and C on the left, right
and bottom of the device also contain an optional Adaptive Input Logic (AIL) element. This logic automatically
aligns incoming data with the clock allowing for easy design of high-speed interfaces. Figure 2-21 shows a simpli-
fied block diagram of the shift register block. The shift block in conjunction with the update and clock divider blocks
automatically handles the hand off between the low-speed and high-speed clock domains.
2-18