m52d16161a Elite Semiconductor Memory Technology Inc., m52d16161a Datasheet
m52d16161a
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m52d16161a Summary of contents
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... DD SS Elite Semiconductor Memory Technology Inc. GENERAL DESCRIPTION The M52D16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, t Blocks data input when L(U)DQM active. M52D16161A LWE LDQM DQi LDQM LWCBR L(U)DQM Input Function after the clock and masks the output ...
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... OL ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 1MHz) ° Symbol C CLK ADD C OUT M52D16161A Value -1.0 ~ 2.6 -1.0 ~ 2.6 - 150 0.7 50 ° C ° Typ Max Unit 1.8 1.9 V 1.8 V +0.3 V DDQ 0 0 ...
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... CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated (min) CCD CCD ≥ (min TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52D16161A ° Version -10 - 0.12 ∞ = 0.1 =15ns 5.5 ∞ 1.5 ∞ =15ns 10 ∞ ...
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... RCD t (min (min) 50 RAS t (max) RAS t (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 M52D16161A ° ) Unit / 0 Vtt =0.5x VDDQ 50 Z0= Unit - 100 CLK 2 CLK 1 CLK ...
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... SAC - SLZ - 7 t SHZ - 8 *All AC parameters are measured from half to half. M52D16161A -15 Unit Note Min Max 15 1000 2 ...
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... LTMODE WT BL LTMODE WT BL Latency mode CLOCK CKE CS RAS CAS WE M52D16161A Address bus Burst Read and Single Write (for Write Through Cache) Mode Register Set x =Don’t care A2-A0 000 001 010 Burst length 011 100 101 110 111 Full page ...
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... Elite Semiconductor Memory Technology Inc PASR DS M52D16161A Address bus Extended Mode Register Set A2-A0 Self Refresh Coverage 000 2 Banks 001 1 Bank (Bank 0, BA=0) 010 1/2 Bank (BA=A10=0) PASR 011 100 101 1/4 Bank (BA=A10=A9=0) 110 111 A6-A5 Driver Strength ...
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... M52D16161A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
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... Entry Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High Logic Low) after the end of burst. RP M52D16161A DQM BA A10/AP A9~A0 Note RAS CAS ...
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... *Note M52D16161A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
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... Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M52D16161A Publication Date : May 2009 Revision : 1.7 12/32 ...
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... Elite Semiconductor Memory Technology Inc M52D16161A ...
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... Qa1 Qa2 Qa3 Qa0 Qa1 Qa3 Qa0 Qa2 Precharge Row Active (A-Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M52D16161A Cb0 Rb Db2 Db0 Db1 *Note4 Db0 Db2 Db1 *Note4 (A- (A-Ban k) ...
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... HIGH Cb0 Qa0 Qb0 Qb1 Qb2 Qa1 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M52D16161A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...
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... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb0 QAa0 QAa1 QAa3 QAa2 Read (B-Bank) Row Active (B-Bank) M52D16161A CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb0 QBb2 QBb3 QAc0 QAc1 QBd0 ...
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... Elite Semiconductor Memory Technology Inc HIGH CBb RBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) (B-Bank) M52D16161A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write ...
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... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52D16161A Publication Date : May 2009 Revision : 1.7 18/32 ...
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... Read with Auto Precharge Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M52D16161A ...
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... Elite Semiconductor Memory Technology Inc M52D16161A ...
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... *Note2 M52D16161A ...
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... Elite Semiconductor Memory Technology Inc M52D16161A ...
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... Row Active (B-Bank) Read with Auto Precharge (A-Bank) M52D16161A * ...
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... Row Active Precharge Active Power-Down Power-down Exit Entry M52D16161A Read Active Power-down Exit Publication Date : May 2009 Revision : 1 ...
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... Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc. M52D16161A Publication Date : May 2009 Revision : 1.7 25/32 ...
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... *Note3 required before exit from self refresh. RAS M52D16161A ...
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... RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52D16161A Publication Date : May 2009 Revision : 1 ...
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... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal extended mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Extended Mode Register Set table. Elite Semiconductor Memory Technology Inc M52D16161A Publication Date : May 2009 Revision : 1.7 28/32 ...
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... Elite Semiconductor Memory Technology Inc. Nom Max - 1.20 0.127 0.203 1.00 1.05 - 0.45 0.35 0.40 - 0.21 0.127 0.16 20.95 21.08 11.76 11.96 10.16 10.29 0.50 0.60 0.80 REF 0.80 BSC - 8 M52D16161A Dimension in inch Min Nom - - 0.002 0.005 0.037 0.039 0.012 - 0.012 0.014 0.005 - 0.004 0.005 0.820 0.825 0.455 0.463 0.394 0.400 0.016 0.020 0.031 REF 0.031 BSC 0 - Publication Date : May 2009 Revision : 1 ...
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... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 6.30 6.40 6.50 0.248 10.00 10.10 10.20 0.394 3.90 9.10 0.65 M52D16161A Dimension in inch Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.252 0.256 0.398 0.402 0.154 0.358 0.026 Publication Date : May 2009 Revision : 1.7 30/32 ...
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... Modify pin name A11 => Correct the voltage of absolute maximum ratings 2. Correct Power Up Sequence for EMRS and add the 2009.05.11 chart of EMRS 3. Add the chart of Deep Power Down Mode 4. Modify rhe description about self refresh opearation M52D16161A Description ; SPEC ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D16161A Publication Date : May 2009 Revision : 1.7 32/32 ...