m52d64322a Elite Semiconductor Memory Technology Inc., m52d64322a Datasheet - Page 5

• Manufacturer Part Number: m52d64322a
• Description: 512k X 32 Bit X 4 Banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

AC OPERATING TEST CONDITIONS (V
Output
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh Command
Number of valid output data
Refresh period(4K cycle)
10.6K
5. A new command may be given t
6. A maximum of eight consecutive AUTO REFRESH commands (with t
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig.1) DC Output Load circuit
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Parameter
@Operating
@Auto refresh
Parameter
1.8V
13.9K
20 pF
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
RFC
DD
=1.8V
after self refresh exit.
±
0.1V,T
Symbol
CAS latency=3
CAS latency=2
A
= 0 C
t
t
t
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
RFC
CDL
RDL
BDL
CCD
MRD
REF
°
(min)
(min)
(min)
(min)
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(max)
Output
~ 70 C
0.9 x V
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
° )
Value
DDQ
(Fig.2) AC Output Load Circuit
DDQ
DDQ
RFCmin
/ 0.2
Z0=50
) can be posted to any given SDRAM,and
Version
100
100
100
-10
20
30
30
50
64
1
2
1
1
2
2
1
Publication Date: Jan. 2009
Revision: 1.4
Vtt =0.5x VDDQ
20 pF
50
M52D64322A
Unit
CLK
CLK
CLK
CLK
CLK
ms
ns
ns
ns
ns
ns
ea
us
ns
Unit
ns
V
V
V
5/46
Note
1 , 5
1
1
1
1
1
2
2
2
3
4
6
-
-