f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet - Page 3

• Manufacturer Part Number: f25l32qa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual And Quad
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Elite Semiconductor Memory Technology Inc.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
HOLD / SIO
SO / SIO
WP / SIO
SI / SIO
Symbol
SCK
V
V
CE
DD
SS
0
1
2
3
Serial Data Input Output 0
Serial Data Input Output 1
Serial Data Input Output 2
Serial Data Input Output 3
High Voltage
CE
Generator
Serial Data Output /
Serial Data Input /
Write Protect /
Power Supply
Chip Enable
Serial Clock
Pin Name
Ground
Hold /
SCK
Register
Command and Conrol Logic
Status
Latch / Counter
Page Address
(SIO
Serial Interface
SI
0
Latch / Counter
)
Byte Address
(SIO
SO
(Preliminary)
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
To provide power.
1
)
(SIO
WP
2
)
Page Buffer
Y-Decoder
Memory
HOLD
(SIO
Array
3
)
Functions
Publication Date: Jan. 2009
Revision: 0.2
F25L32QA
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