zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 60

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note: [n] denotes output offset frame pulse from 0 to 2.
15 - 11
9 - 2
1 - 0
Bit
10
External Read/Write Address: 0005
Reset Value: 0000
15
0
14
0
FOF[n]OFF7 - 0
FOF[n]C1 - 0
Unused
FP19EN
13
Name
0
H
12
0
11
0
Reserved. In normal functional mode, these bits MUST be set to zero.
19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only)
This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to zero.
When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to
19.44 MHz without channel offset.
When this bit is low, FPo_OFF2 is output frame pulse with channel offset.
FPo_OFF[n] Channel Offset
The binary value of these bits refers to the channel offset from original frame bound-
ary. Permitted channel offset values depend on bits 1-0 of this register.
FPo_OFF[n] Control bits
Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
FOF[n]C
FP19
H
EN
10
1-0
- 0007
00
01
10
11
FOF[n]
OFF7
H
9
Data Rate
(Mbps)
16.384
2.048
4.096
8.192
FOF[n]
Zarlink Semiconductor Inc.
OFF6
8
ZL50019
FOF[n]
OFF5
one 16.384 MHz
clock
one 16.384 MHz
clock
one 4.096 MHz clock
one 8.192 MHz clock
60
7
Pulse Cycle Width
FPo_OFF[n]
FOF[n]
OFF4
6
Description
FOF[n]
OFF3
5
FOF[n]
FOF[n]OFF7 - 0
OFF2
Channel Offset
4
Permitted
0 - 127
0 - 255
0 - 31
0 - 63
FOF[n]
OFF1
3
FOF[n]
OFF0
2
Polarity
Control
FPO0P
FPO1P
FPO2P
FPO2P
FOF[n]
Data Sheet
C1
1
FPO0POS
FPO1POS
FPO2POS
FPO2POS
Position
Control
FOF[n]
C0
0