zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 64

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Reset Value: 0000
External Read/Write Address: 0041
15-12
11 - 9
8 - 6
Bit
15
0
14
0
R3F2 - 0
R2F2 - 0
Unused
Name
H
13
0
Reserved
In normal functional mode, these bits MUST be set to zero.
Reference 3 Frequency Bits
When the RFRE bit of the DPLLCR register is high, these bits are used to select the
REF3 input frequency. When the RFRE bit is low, these bits are ignored.
Reference 2 Frequency Bits: When the RFRE bit of the DPLLCR register is high, these
bits are used to select the REF2 input frequency. When the RFRE bit is low, these bits
are ignored.
12
0
Table 29 - Reference Frequency Register (RFR) Bits
H
R3F2
11
R3F1
10
R3F2
R2F2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R3F0
9
Zarlink Semiconductor Inc.
ZL50019
R2F2
R3F1
R2F1
8
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
64
R2F1
7
R3F0
R2F0
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R2F0
6
REF 3 Input Frequency
REF 2 Input Frequency
R1F2
5
16.384 MHz
16.384 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
19.44 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
19.44 MHz
Reserved
Reserved
R1F1
8 kHz
8 kHz
4
R1F0
3
R0F2
2
R0F1
Data Sheet
1
R0F0
0
(see